On 19/08/18 12:48, Chuanhong Guo wrote:
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.
This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong
From: Marcus Comstedt
Signed-off-by: Marcus Comstedt
---
lua/ubus.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/lua/ubus.c b/lua/ubus.c
index 00d9e00..4da3c80 100644
--- a/lua/ubus.c
+++ b/lua/ubus.c
@@ -111,6 +111,17 @@ ubus_lua_parse_blob(lua_State *L, struct blob_attr
From: Marcus Comstedt
Hi.
I noticed that using luci.util.ubus() does not work correctly when the
called function returned doubles (only nils are returned). This patch
adds the capability of correctly forwarding BLOBMSG_TYPE_DOUBLE to
lua.
It is still not possible to send parameters of type
BLO
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.
This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMA
Hi,
On 8/21/18 8:31 AM, Stefan Lippers-Hollmann wrote:
> While this passes the version check, the appended git hash does break
> later on in the flashing process - so at the moment only the numerical
> revision (of DISTRIB_REVISION='r7890-40eb9bda44') seems to be safe:
>
> RAS_VERSION := "V1.99(
It is based on Chuanhong Guo work.
PCI interrupt controller is not part of PCI. It is a part of reset controller
with 0x18060018, 0x1806001c control registers.
This should fix a bug with one IRQ for all PCI devices and also handle the
PCI_CORE interrupt.
I am not sure that this kind of cascadin
Performance tests look good too.
вт, 21 авг. 2018 г. в 17:59, Dmitry Tunin :
>
> It is based on Chuanhong Guo work.
>
> PCI interrupt controller is not part of PCI. It is a part of reset controller
> with 0x18060018, 0x1806001c control registers.
>
> This should fix a bug with one IRQ for all PCI d
Hi!
Comments inline:
Dmitry Tunin 于2018年8月21日周二 下午10:59写道：
>
> It is based on Chuanhong Guo work.
>
> PCI interrupt controller is not part of PCI. It is a part of reset controller
> with 0x18060018, 0x1806001c control registers.
>
> This should fix a bug with one IRQ for all PCI devices and also h
> > This should fix a bug with one IRQ for all PCI devices and also handle the
> > PCI_CORE interrupt.
> No it doesn't. Assigning it in dts doesn't mean that we "handled" it.
> But I still like this patch because it's doing a cleanup of the messy code.
I am still not very competent in the IRQ han
Dmitry Tunin 于2018年8月22日周三 上午12:26写道：
> I am still not very competent in the IRQ handling. I thought that if we set
> interrupts = <4>; and the new partent, your "case 4:" may work.
We have it there because it appears in datasheet. But we don't need it
to work unless we know what it's used for.
>
Hi
On 2018-08-21, David Bauer wrote:
> On 8/21/18 8:31 AM, Stefan Lippers-Hollmann wrote:
> > While this passes the version check, the appended git hash does break
> > later on in the flashing process - so at the moment only the numerical
> > revision (of DISTRIB_REVISION='r7890-40eb9bda44') seem
> > They are similar. I used that code as an example, but the
> > irq-ath79-pci has your mask/unmask for pci with reading the registers.
> > It is possible to make one driver for both, but is it really needed?
> It helps reducing code duplication.
If we completely drop that PCI_CORE IRQ that we ar
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