Hi
I've just checked dir300b1/dir620a1 (rt3050/rt3052) - 40MHz both. 21bit(PLL
bypass) of syscfg = 0. So it's board specific.
12.11.2012, 17:29, "Gabor Juhos" :
> 2012.11.12. 10:16 keltezéssel, Daniel Golle írta:
>
>> Hi!
>>
>> Thank you for clarifying this one! That was probably a life saver.
2012.11.12. 10:16 keltezéssel, Daniel Golle írta:
> Hi!
>
> Thank you for clarifying this one! That was probably a life saver. I should
> have
> google'd the acronym XTAL=Crystal...
>
> So: I'm wondering why it's done in SwitchChannel and not during initialization
> in the vendor driver (as it w
Hi!
Thank you for clarifying this one! That was probably a life saver. I should have
google'd the acronym XTAL=Crystal...
So: I'm wondering why it's done in SwitchChannel and not during initialization
in the vendor driver (as it won't ever change in run-time, if I got it right
now...)
If this de
Hi, Daniel
And no, No, NO! :)
I pooly explain or you don't pay attention. Xtal20/40MHz external clock/tick
generator have no direct relation to HT20/HT40
but precision of channel frequency only. So for that case we use corrected
frequency rf_vals table. And Xtal20/40MHz really must
be read fro
Recent Ralink RFs need different rf_vals depending on whether HT20 or HT40 is
being used.
Signed-off-by: Daniel Golle
create mode 100644 package/mac80211/patches/623-differentiate-rf_vals.patch
diff --git a/package/mac80211/patches/622-rt2x00-fix-rt3352-ext-pa.patch
b/package/mac80211/patches
