On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit wrote:
>> +#define RTL8366RB_POWER_SAVE 0x21
> Typically PHY register addresses are 5 bits wide, is 0x21 correct
> and I miss something?
If it is correct I don't know, but it appears in the vendor
code:
/*Power Saving*/
#define RTL8368S_POWER_SA
Am 29.05.2018 um 22:01 schrieb Linus Walleij:
> On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit wrote:
>
>>> +#define RTL8366RB_POWER_SAVE 0x21
>
>> Typically PHY register addresses are 5 bits wide, is 0x21 correct
>> and I miss something?
>
> If it is correct I don't know, but it appears in t
Am 28.05.2018 um 19:47 schrieb Linus Walleij:
> The RTL8366RB is an ASIC with five internal PHYs for
> LAN0..LAN3 and WAN. The PHYs are spawn off the main
> device so they can be handled in a distributed manner
> by the Realtek PHY driver. All that is really needed
> is the power save feature enabl
On Tue, May 29, 2018 at 10:01:14PM +0200, Linus Walleij wrote:
> On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit wrote:
>
> >> +#define RTL8366RB_POWER_SAVE 0x21
>
> > Typically PHY register addresses are 5 bits wide, is 0x21 correct
> > and I miss something?
Heiner is correct, MDIO only suppo
