> > If the DSA subsystem could handle the "merging" instead and also call
> > port_mdb_add/port_mdb_del as appropriate for multicast router ports, the
> > individual drivers wouldn't have to deal with this particular issue at all.
> >
> > > As a way to fix a bug quickly and get correct behavior, I
> > I just took a quick look at the driver. It allocates and maps rx buffers
> > that can cover a packet size of BGMAC_RX_MAX_FRAME_SIZE = 9724.
> > This seems rather excessive, especially since most people are going to use
> > a MTU of 1500.
> > My proposal would be to add support for making rx
> you'll see that most used functions are:
> v7_dma_inv_range
> __irqentry_text_end
> l2c210_inv_range
> v7_dma_clean_range
> bcma_host_soc_read32
> __netif_receive_skb_core
> arch_cpu_idle
> l2c210_clean_range
> fib_table_lookup
There is a lot of cache management functions here. Might sound odd,
On Sat, Jun 08, 2019 at 04:06:54AM -0500, Daniel Santos wrote:
> Hello,
Hi Daniel
As Daniel Golle pointed out, swconfig is an openwrt only
thing. Mainline people on netdev are unlikely to help you much. If you
do however decide to work on the mainline DSA driver, people here will
offer help, answ
> > +Realtek SMI-based Switches
> > +==
> > +
> > +The SMI "Simple Management Interface" is a two-wire protocol using
>
> At least for some other Realtek chips, the documentation I find says the
> S stands for Serial. And Wikipedia says SMI is the same thing as MDIO.
>
>
On Mon, May 28, 2018 at 07:47:49PM +0200, Linus Walleij wrote:
> The RTL8366RB is an ASIC with five internal PHYs for
> LAN0..LAN3 and WAN. The PHYs are spawn off the main
> device so they can be handled in a distributed manner
> by the Realtek PHY driver. All that is really needed
> is the power s
On Tue, May 29, 2018 at 10:01:14PM +0200, Linus Walleij wrote:
> On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit wrote:
>
> >> +#define RTL8366RB_POWER_SAVE 0x21
>
> > Typically PHY register addresses are 5 bits wide, is 0x21 correct
> > and I miss something?
Heiner is correct, MDIO only suppo
; Set it to zero for the time being and drop a comment so
> people know what is going on if they run into trouble. This
> "mode zero" works fine with the D-Link DIR-685 with
> RTL8366RB.
>
> Signed-off-by: Linus Walleij
Reviewed-by: Andrew Lunn
Andrew
___
gned-off-by: Linus Walleij
Reviewed-by: Andrew Lunn
Andrew
___
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
On Fri, Jul 13, 2018 at 11:19:35PM +0200, Linus Walleij wrote:
> Subject: [PATCH 2/3 v4] ARM: dts: Att Vitesse G5e switch to the Gemini SQ201
Hi Linus
s/Att/Add in the subject line.
> Signed-off-by: Linus Walleij
Reviewed-by: Andrew Lunn
On Fri, Jul 13, 2018 at 11:19:34PM +0200, Linus Walleij wrote:
> This sets up the ethernet interface and PHY for the
> WAN ethernet port which uses a Marvell PHY.
>
> Signed-off-by: Linus Walleij
Reviewed-by: Andrew Lunn
Andrew
___
On Wed, Jul 11, 2018 at 09:47:18PM +0200, Linus Walleij wrote:
> This sets up the ethernet interface and PHY for the
> WAN ethernet port which uses a Marvell PHY.
>
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v2->v3:
> - No changes, just resending.
> ChangeLog v1->v2:
> - Rename wrongly name
On Sun, Jul 08, 2018 at 09:53:39PM +0200, Linus Walleij wrote:
> On Fri, Jul 6, 2018 at 12:37 AM Andrew Lunn wrote:
>
> > arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> >
> > ð0 {
> > phy-mode = "rgmii-id";
> >
> > > + vsc: port@6 {
> > > + reg = <6>;
> > > + label = "cpu";
> > > + ethernet = <&gmac1>;
> > > + phy-mode = "rgmii";
> > >
On Wed, Jul 04, 2018 at 09:17:59PM +0200, Linus Walleij wrote:
> The Storlink Gemini324 EV-Board also known as Storm
> Semiconductor SL93512R_BRD is ground zero for the Gemini
> devices. We add a device tree so we can support it, it
> turns out to be pretty trivial.
>
> Signed-off-by: Linus Wallei
On Wed, Jul 04, 2018 at 09:17:57PM +0200, Linus Walleij wrote:
> This sets up the ethernet interface and PHY for the
> WAN ethernet port which uses a Marvell PHY.
>
> Signed-off-by: Linus Walleij
> ---
> arch/arm/boot/dts/gemini-sq201.dts | 85 ++
> 1 file changed, 85
On Tue, May 29, 2018 at 10:49:46AM +0200, Linus Walleij wrote:
> On Mon, May 28, 2018 at 8:20 PM, Andrew Lunn wrote:
> > On Mon, May 28, 2018 at 07:47:48PM +0200, Linus Walleij wrote:
> >> This is a second RFC version of the DSA driver for Realtek
> >> RT
On Mon, May 28, 2018 at 07:47:48PM +0200, Linus Walleij wrote:
> This is a second RFC version of the DSA driver for Realtek
> RTL8366x especially RTL8366RB.
>
> I've been beating my head against this one and I'm not really
> clear on why my ethernet frames are not coming through to the
> CPU port
18 matches
Mail list logo
