Qiang Wang wrote:
> hello, all
> sorry, I repeat the message again because nobody answer it.
> I test the JTAG interface with Logic Analyze Device, today .
> I found some fact as below.
>
> 1. the jtag_khz will affect the TCK of JTAG.
> When 6000, It will be 6MHz of the TCK, when 3000, the TCK wil
hello, all
sorry, I repeat the message again because nobody answer it.
I test the JTAG interface with Logic Analyze Device, today .
I found some fact as below.
1. the jtag_khz will affect the TCK of JTAG.
When 6000, It will be 6MHz of the TCK, when 3000, the TCK will be 3MHz.
But if I change the j
hello,
I use the following configuration. Does it mean that , the system
reset and t reset signal will be assert when openocd started.
# The configuration of the reset signals available on
# the JTAG interface AND the target.
reset_config trst_and_srst
best regards
wangqiang
_
