On 09/29/2011 09:40 AM, Michel JAOUEN wrote:
Hello,
I implemented the flush of L1 and L2 cache for cortex_a.
I added the support of phys memory access through dap apsel 1,
(for this access, a flush is performed, and mmu is disabled)
I also implement va_to_pa mechanism for virt_to_phys.
For
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