[Openocd-development] Tags

When I run git describe now I get v0.4.0-973-g0d7a948 rather than a v0.5.0-rc2-. Is that intentional? I think it's nice that we stick to v0.4.0- until v0.5.0- goes out of the door. I have no particular opinion, except it should be by choice and not by accident :-) -- Øyvind Harboe

Re: [Openocd-development] Last call before release

Hi Rordrigo, it's too late for this release, we're just waiting for the release to go out of the door, I don't think there are any issues we intend to fix at this point. -- Øyvind Harboe - Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 87 40 27 http

Re: [Openocd-development] Last call before release

I submitted these patches a couple weeks ago, i guess everybody was too busy with the release... Could they be added? Thanks! On Wed, Aug 3, 2011 at 7:34 AM, Andreas Fritiofson wrote: > On Wed, Aug 3, 2011 at 3:32 PM, Tomek CEDRO wrote: >> >> Hello Jean, please provide full featured RC package

Re: [Openocd-development] Clock setup for STM32F107

Hi, > Thanks for testing the patches. So, a significant speed-up (~50%) due to > the async patches, great. I believe the actual flashing is now mostly > limited by flash write speed of the STM32F1x (~39 KiB/s => about 1.2 > seconds for your file) and that there's not much more that can be done >

Re: [Openocd-development] [PATCH 5/5] stm32x: use async algorithm in flash programming routine

Repost, it didn't make it to the list. On Thu, Aug 4, 2011 at 8:39 PM, Andreas Fritiofson < andreas.fritiof...@gmail.com> wrote: > On Sat, Jul 30, 2011 at 6:44 PM, Øyvind Harboe wrote: > >> Hi Andreas, >> >> could you maintain these patches in an official fork of openocd and >> post a pull reques

Re: [Openocd-development] [PATCH] Automatically generate ChangeLog from git log for release tarball

On Wed, Aug 3, 2011 at 5:48 PM, Spencer Oliver wrote: > On 3 August 2011 15:00, Andreas Fritiofson > wrote: > > If the pipe method work, fine. However, looking through the git2cl code > it > > apparently assumes git log is run with LC_ALL=C and that wouldn't be the > > case with the latest incar

Re: [Openocd-development] Clock setup for STM32F107

On Thu, Aug 4, 2011 at 5:12 PM, Simon Barner wrote: > I applied the patches 1/5 - 5/5 against my fixed ARM-JTAG-EW driver > and yield now (STM32F107, JTAG @ 6 MHz). Also, debugging the target > seems to work decently. > > flash erase_address 0x0800 0x4 > erased address 0x0800 (length

Re: [Openocd-development] Tutorial Material on Flash Drivers

Cool :-) Congrautlations Jim! We wanted to do something like that as more general wiki with Drasko, so now we have a place to develop :-) Best regards, Tomek -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info ___ Openocd-development mailing list Openocd-d

[Openocd-development] Tutorial Material on Flash Drivers

Based on my need for a flash driver for a new chip, I have created some tutorial material on creating flash drivers for OpenOCD. This is work-in-progress as I experiment and learn more. Inspired by an Open Source Software Engineering class at Portland State University, I have posted some code a

Re: [Openocd-development] Clock setup for STM32F107

Andreas, list, On 04.08.2011 09:46, Simon Barner wrote: > On 04.08.2011 09:30, Simon Barner wrote: >> Some further benchmarks (OpenOCD compiled without any additional logging): >> >> @ 32 KHz: 1.9 kb/s >> @ 64 KHz: 3.4 kb/s >> @ 125 KHz: 5.6 kb/s >> @ 250 KHz: 8.1 kb/s >> @ 500 KHz: 10.2 kb/s >> @

Re: [Openocd-development] Jlink SRST pin value

Additional information: I think the jlink can not communicate with my CPU msm7x27A (when CPU is in the reset state) Because now, the "reset" and "halt" command is working. But the "reset halt" and "reset init" isn't. When execute "reset halt", it will display some errors: > reset halt JTAG tap: ms

[Openocd-development] Jlink SRST pin value

Hi, I am a newbie of openocd. I am using JLink to debug a ARM926ejs CPU. During startup of openocd, it will use EMU_CMD_GET_STATE command to get all the pins state of jlink. On a working board, it gets TMS = 0 SRST = 0 TRST = 0 On a no-working board, it gets TMS = 0 SRST = 1 TRST = 0, (then it w

Re: [Openocd-development] Clock setup for STM32F107

On 04.08.2011 09:30, Simon Barner wrote: > Some further benchmarks (OpenOCD compiled without any additional logging): > > @ 32 KHz: 1.9 kb/s > @ 64 KHz: 3.4 kb/s > @ 125 KHz: 5.6 kb/s > @ 250 KHz: 8.1 kb/s > @ 500 KHz: 10.2 kb/s > @ 1MHz: 11.8 kb/s > @ 2MHz: 12.9 kb/s > @ 4MHz: 13.4 kb/s > @ 6MHz:

[Openocd-development] Clock setup for STM32F107

Hi, inspired by this post, I created a reset-init script that initializes the system clock for the STM32F107 (connectivity line) and sets the JTAG speed to 6 MHz. Currently, I source it in my custom configuration s