On Thu, Jul 14, 2011 at 6:45 PM, Maxim Cournoyer
wrote:
> **
> Hello Rodrigo & OpenOCD comrades!
>
> Le jeudi 07 juillet 2011 à 14:55 -0700, Rodrigo Rosa a écrit :
>
> the c part of your code was very useful. i'm was the telnet port, and
> ignoring the output i did not care about.
> now with the g
Hi all,
I have a following problem : I have a slave CPU which is under
constant reset in a multicore SoC. This slave CPU is woken up by the
write to certain register bu main CPU.
Then reset from slave CPU is removed and it can be halted, written to, etc.
My problem is that I created two targets in
Hi all,
I have noticed that accessing (more precise: writing) memory
byte-by-byte on MIPS32 targets is currently borken.
Temporary array allocated for endianess swap replaces the contenst of
the buffer. However, this temporary array is set-up only for hword and
word accesses.
This, in the case of
