Re: [PATCH 2/2] drm/nouveau: DRM_NOUVEAU_SET_ZCULL_CTXSW_BUFFER

2025-07-31 Thread M Henning
On Fri, Mar 28, 2025 at 7:48 AM Danilo Krummrich wrote: > > On Thu, Mar 27, 2025 at 03:01:54PM -0400, M Henning wrote: > > On Thu, Mar 27, 2025 at 9:58 AM Danilo Krummrich wrote: > > > > > > On Fri, Mar 21, 2025 at 07:00:57PM -0400, M Henning wrote: > > > > This is a pointer in the gpu's virtual

Re: [PATCH 2/2] drm/nouveau: DRM_NOUVEAU_SET_ZCULL_CTXSW_BUFFER

2025-04-04 Thread Danilo Krummrich
On Wed, Mar 12, 2025 at 05:36:15PM -0400, Mel Henning wrote: > diff --git a/include/uapi/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h Same here, please split the uAPI change in a separate commit. > index 33361784eb4e..e9638f4dd7e6 100644 > --- a/include/uapi/drm/nouveau_drm.h > +++ b/includ

Re: [PATCH 2/2] drm/nouveau: DRM_NOUVEAU_SET_ZCULL_CTXSW_BUFFER

2025-03-28 Thread Danilo Krummrich
On Thu, Mar 27, 2025 at 03:01:54PM -0400, M Henning wrote: > On Thu, Mar 27, 2025 at 9:58 AM Danilo Krummrich wrote: > > > > On Fri, Mar 21, 2025 at 07:00:57PM -0400, M Henning wrote: > > > This is a pointer in the gpu's virtual address space. It must be > > > aligned according to ctxsw_align and

Re: [PATCH 2/2] drm/nouveau: DRM_NOUVEAU_SET_ZCULL_CTXSW_BUFFER

2025-03-27 Thread M Henning
On Thu, Mar 27, 2025 at 9:58 AM Danilo Krummrich wrote: > > On Fri, Mar 21, 2025 at 07:00:57PM -0400, M Henning wrote: > > This is a pointer in the gpu's virtual address space. It must be > > aligned according to ctxsw_align and be at least ctxsw_size bytes > > (where those values come from the no

Re: [PATCH 2/2] drm/nouveau: DRM_NOUVEAU_SET_ZCULL_CTXSW_BUFFER

2025-03-27 Thread Danilo Krummrich
On Fri, Mar 21, 2025 at 07:00:57PM -0400, M Henning wrote: > This is a pointer in the gpu's virtual address space. It must be > aligned according to ctxsw_align and be at least ctxsw_size bytes > (where those values come from the nouveau_abi16_ioctl_get_zcull_info > structure). I'll change the desc

Re: [PATCH 2/2] drm/nouveau: DRM_NOUVEAU_SET_ZCULL_CTXSW_BUFFER

2025-03-23 Thread M Henning
This is a pointer in the gpu's virtual address space. It must be aligned according to ctxsw_align and be at least ctxsw_size bytes (where those values come from the nouveau_abi16_ioctl_get_zcull_info structure). I'll change the description to say that much. Yes, this is GEM-backed. I'm actually no