Handling an Extra Signal at PHY Reset

nk about how we could solve this issue? Do you see other options that I missed here? Cheers and thanks in advance, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com

Re: [PATCH RESEND net] net: phy: xgmiitorgmii: Support generic PHY status read

Hi, On Fri, 2019-02-15 at 10:53 -0800, Florian Fainelli wrote: > On 2/15/19 10:34 AM, Paul Kocialkowski wrote: > > As I was mentionning to Andrew in the initial submission of this patch, > > this driver is a bit unusual since it represents a GMII to RGMII > > bridge, so it

Re: Handling an Extra Signal at PHY Reset

Hi, On Tue, 2019-02-19 at 10:36 +0100, Thomas Petazzoni wrote: > Hello Paul, > > On Tue, 19 Feb 2019 10:14:20 +0100 > Paul Kocialkowski wrote: > > > We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a > > CONFIG pin that must be connected to one o

Re: Handling an Extra Signal at PHY Reset

Hi Andrew, On Tue, 2019-02-19 at 14:36 +0100, Andrew Lunn wrote: > On Tue, Feb 19, 2019 at 10:14:20AM +0100, Paul Kocialkowski wrote: > > Hi, > > > > We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a > > CONFIG pin that must be connected to one o

Re: Handling an Extra Signal at PHY Reset

Hi Andrew, On Thu, 2019-02-21 at 02:49 +0100, Andrew Lunn wrote: > On Tue, Feb 19, 2019 at 10:14:20AM +0100, Paul Kocialkowski wrote: > > Hi, > > > > We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a > > CONFIG pin that must be connected to one o

Re: Handling an Extra Signal at PHY Reset

Hi Florian, On Tue, 2019-02-19 at 08:07 -0800, Florian Fainelli wrote: > > On February 19, 2019 1:14:20 AM PST, Paul Kocialkowski > wrote: > > Hi, > > > > We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a > > CONFIG pin that must be conn

Re: [PATCH RESEND net] net: phy: xgmiitorgmii: Support generic PHY status read

y. Currently, the PHY mode has to be set to GMII for the MAC to be configured correctly, but the PHY also gets this information while it should be told that RGMII is in use. This doesn't seem to play a big role in PHY configuration though, but it's still inadequate. What do you think? -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com

Re: Handling an Extra Signal at PHY Reset

having it connected to the PTP clock instead of the LED pin does not seem to change the address we're getting. We'll stick with that solution, since it's the least invasive one. Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com

[PATCH] net: phy: xgmiitorgmii: Support generic PHY status read

: Paul Kocialkowski --- drivers/net/phy/xilinx_gmii2rgmii.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index 74a8782313cf..bd6084e315de 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b

Re: [PATCH] net: phy: xgmiitorgmii: Support generic PHY status read

Hi, On Fri, 2019-02-15 at 17:23 +0100, Andrew Lunn wrote: > On Fri, Feb 15, 2019 at 05:17:08PM +0100, Paul Kocialkowski wrote: > > Some PHY drivers like the generic one do not provide a read_status > > callback on their own but rely on genphy_read_status being called > > di

[PATCH RESEND net] net: phy: xgmiitorgmii: Support generic PHY status read

: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support") Signed-off-by: Paul Kocialkowski --- Added Fixes tag and net label for resend. drivers/net/phy/xilinx_gmii2rgmii.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drive

Re: [PATCH RESEND net] net: phy: xgmiitorgmii: Support generic PHY status read

Hi, On Fri, 2019-02-15 at 09:38 -0800, Florian Fainelli wrote: > On 2/15/19 8:32 AM, Paul Kocialkowski wrote: > > Some PHY drivers like the generic one do not provide a read_status > > callback on their own but rely on genphy_read_status being called > > directly. > >