Hi Russell, Andrew,
On Fri, 20 Nov 2020 14:55:17 +0100
Andrew Lunn wrote:
>On Fri, Nov 20, 2020 at 10:25:38AM +, Russell King - ARM Linux admin wrote:
>> On Fri, Nov 20, 2020 at 10:36:01AM +0100, Maxime Chevallier wrote:
>> > So maybe we could be a bit more generic, with something along th
On Fri, Nov 20, 2020 at 10:25:38AM +, Russell King - ARM Linux admin wrote:
> On Fri, Nov 20, 2020 at 10:36:01AM +0100, Maxime Chevallier wrote:
> > So maybe we could be a bit more generic, with something along these lines :
> >
> > ethernet-phy@0 {
> > ...
> >
> > mdi {
>
On Fri, Nov 20, 2020 at 10:25, Russell King - ARM Linux admin
wrote:
> On Fri, Nov 20, 2020 at 10:36:01AM +0100, Maxime Chevallier wrote:
>> So maybe we could be a bit more generic, with something along these lines :
>>
>> ethernet-phy@0 {
>> ...
>>
>> mdi {
>> p
On Fri, Nov 20, 2020 at 10:36:01AM +0100, Maxime Chevallier wrote:
> So maybe we could be a bit more generic, with something along these lines :
>
> ethernet-phy@0 {
> ...
>
> mdi {
> port@0 {
> media = "10baseT", "100baseT", "1000baseT";
>
Hi Tobias,
On Fri, 20 Nov 2020 01:11:12 +0100
Tobias Waldekranz wrote:
>On Thu, Nov 19, 2020 at 23:16, Russell King - ARM Linux admin
> wrote:
>> On Thu, Nov 19, 2020 at 11:43:39PM +0100, Tobias Waldekranz wrote:
>>> On Thu, Nov 19, 2020 at 16:24, Maxime Chevallier
>>> wrote:
>>> > I don'
On Fri, Nov 20, 2020 at 00:40, Russell King - ARM Linux admin
wrote:
> I think you're advocating calling the fiber interface "SGMII", which
> would be totally wrong.
>
> SGMII is a Cisco modification of 802.3 1000base-X to allow 10M and 100M
> speeds to be used over a single serdes lane in each d
On Fri, Nov 20, 2020 at 01:00, Andrew Lunn wrote:
>> E.g. at Westermo we make switches with M12/M12X connectors [1] that
>> sometimes have a 1G PHY behind a 2-pair M12 connector (for complicated
>> legacy reasons). In such cases we have to remove 1000-HD/FD from the
>> advertised link modes. Being
On Fri, Nov 20, 2020 at 01:11:12AM +0100, Tobias Waldekranz wrote:
> On Thu, Nov 19, 2020 at 23:16, Russell King - ARM Linux admin
> wrote:
> > On Thu, Nov 19, 2020 at 11:43:39PM +0100, Tobias Waldekranz wrote:
> >> On Thu, Nov 19, 2020 at 16:24, Maxime Chevallier
> >> wrote:
> >> > I don't thi
On Thu, Nov 19, 2020 at 23:16, Russell King - ARM Linux admin
wrote:
> On Thu, Nov 19, 2020 at 11:43:39PM +0100, Tobias Waldekranz wrote:
>> On Thu, Nov 19, 2020 at 16:24, Maxime Chevallier
>> wrote:
>> > I don't think we have a way to distinguish from the DT if we are in
>> > SGMII-to-Fibre or
> E.g. at Westermo we make switches with M12/M12X connectors [1] that
> sometimes have a 1G PHY behind a 2-pair M12 connector (for complicated
> legacy reasons). In such cases we have to remove 1000-HD/FD from the
> advertised link modes. Being able to describe that in the DT with
> something like:
On Thu, Nov 19, 2020 at 11:43:39PM +0100, Tobias Waldekranz wrote:
> On Thu, Nov 19, 2020 at 16:24, Maxime Chevallier
> wrote:
> > I don't think we have a way to distinguish from the DT if we are in
> > SGMII-to-Fibre or in SGMII-to-{Copper + Fibre}, since the description is
> > the same, we don'
On Thu, Nov 19, 2020 at 16:24, Maxime Chevallier
wrote:
> I don't think we have a way to distinguish from the DT if we are in
> SGMII-to-Fibre or in SGMII-to-{Copper + Fibre}, since the description is
> the same, we don't have any information in DT about wether or not the
> PHY is wired to a Copp
Hi Andrew,
On Thu, 19 Nov 2020 16:16:41 +0100
Andrew Lunn wrote:
>Hi Maxime
>
>> The way this works is that the PHY is internally configured by chaining
>> 2 internal PHYs back to back. One PHY deals with the Host interface and
>> is configured as an SGMII to QSGMII converter (the QSGMII is only
Hello Russell,
On Thu, 19 Nov 2020 14:55:00 +
Russell King - ARM Linux admin wrote:
>On Thu, Nov 19, 2020 at 03:22:46PM +0100, Maxime Chevallier wrote:
>> Hello everyone,
>>
>> I'm reaching out to discuss an issue I'm currently having, while working
>> on a Marvell 88E1543 PHY.
>>
>> This
On Thu, Nov 19, 2020 at 02:55:00PM +, Russell King - ARM Linux admin wrote:
> On Thu, Nov 19, 2020 at 03:22:46PM +0100, Maxime Chevallier wrote:
> > Hello everyone,
> >
> > I'm reaching out to discuss an issue I'm currently having, while working
> > on a Marvell 88E1543 PHY.
> >
> > This PHY
Hi Maxime
> The way this works is that the PHY is internally configured by chaining
> 2 internal PHYs back to back. One PHY deals with the Host interface and
> is configured as an SGMII to QSGMII converter (the QSGMII is only used
> from within the PHY), and the other PHY acts as the Media-side PH
On Thu, Nov 19, 2020 at 03:22:46PM +0100, Maxime Chevallier wrote:
> Hello everyone,
>
> I'm reaching out to discuss an issue I'm currently having, while working
> on a Marvell 88E1543 PHY.
>
> This PHY is very similar to the 88E1545 we already support upstream, but
> with an added "dual-port mod
Hello everyone,
I'm reaching out to discuss an issue I'm currently having, while working
on a Marvell 88E1543 PHY.
This PHY is very similar to the 88E1545 we already support upstream, but
with an added "dual-port mode" feature that I'm currently using in a
project, and that might be interesting t
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