On Sat, Jul 18, 2020 at 11:21:26AM +, Martin Rowe wrote:
> On Sat, 18 Jul 2020 at 10:13, Russell King - ARM Linux admin
> wrote:
> > Okay, on top of those changes, please also add this:
>
> "in-band-status" plus your chip.c patch works; I can now ping from the GT 8K.
Great, and your kernel m
On Sat, 18 Jul 2020 at 10:13, Russell King - ARM Linux admin
wrote:
> Okay, on top of those changes, please also add this:
"in-band-status" plus your chip.c patch works; I can now ping from the GT 8K.
$ dmesg |grep f400
mvpp2 f400.ethernet: using 8 per-cpu buffers
mvpp2 f400.ethernet
On Sat, Jul 18, 2020 at 09:43:47AM +, Martin Rowe wrote:
> On Sat, 18 Jul 2020 at 08:50, Russell King - ARM Linux admin
> wrote:
> > Sorry, it should have been ``managed = "in-band-status";'' rather than
> > just "in-band".
>
> Below are the outputs with "in-band-status". It functions the sam
On Sat, 18 Jul 2020 at 08:50, Russell King - ARM Linux admin
wrote:
> Sorry, it should have been ``managed = "in-band-status";'' rather than
> just "in-band".
Below are the outputs with "in-band-status". It functions the same as
not reverting the patch; interface comes up, when bridged the two
ph
On Sat, Jul 18, 2020 at 02:37:41AM +, Martin Rowe wrote:
> On Fri, 17 Jul 2020 at 21:26, Russell King - ARM Linux admin
> wrote:
> > Both ends really need to agree, and I'd suggest cp1_eth2 needs to drop
> > the fixed-link stanza and instead use ``managed = "in-band";'' to be
> > in agreement
On Fri, 17 Jul 2020 at 21:26, Russell King - ARM Linux admin
wrote:
> Both ends really need to agree, and I'd suggest cp1_eth2 needs to drop
> the fixed-link stanza and instead use ``managed = "in-band";'' to be
> in agreement with the configuration at the switch.
>
> Martin, can you modify
> arch
On Fri, Jul 17, 2020 at 09:42:37PM +0200, Andrew Lunn wrote:
> On Fri, Jul 17, 2020 at 07:51:19PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jul 17, 2020 at 12:50:07PM +, Martin Rowe wrote:
> > > On Fri, 17 Jul 2020 at 09:22, Russell King - ARM Linux admin
> > > wrote:
> > > >
On Fri, Jul 17, 2020 at 07:51:19PM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jul 17, 2020 at 12:50:07PM +, Martin Rowe wrote:
> > On Fri, 17 Jul 2020 at 09:22, Russell King - ARM Linux admin
> > wrote:
> > > The key file is /sys/kernel/debug/mv88e6xxx.0/regs - please send the
> >
On Fri, Jul 17, 2020 at 12:50:07PM +, Martin Rowe wrote:
> On Fri, 17 Jul 2020 at 09:22, Russell King - ARM Linux admin
> wrote:
> > The key file is /sys/kernel/debug/mv88e6xxx.0/regs - please send the
> > contents of that file.
>
> $ cat regs.broken
> GLOBAL GLOBAL2 SERDES 01
On Fri, 17 Jul 2020 at 09:22, Russell King - ARM Linux admin
wrote:
> The key file is /sys/kernel/debug/mv88e6xxx.0/regs - please send the
> contents of that file.
$ cat regs.broken
GLOBAL GLOBAL2 SERDES 012345
0: c800 0 9e07 9e4f 100f 100f 9e4f 170b
On Fri, Jul 17, 2020 at 05:56:22AM +, Martin Rowe wrote:
> On Sun, 12 Jul 2020 at 13:26, Russell King - ARM Linux admin
> wrote:
> > If it is a port issue, that should help pinpoint it - if it's a problem
> > with the CPU port configuration, then ethtool can't read those registers
> > (and the
On Sun, 12 Jul 2020 at 13:26, Russell King - ARM Linux admin
wrote:
> If you have machine A with address 192.168.2.1/24 on lan1 and machine B
> with address 192.168.2.2/24 on lan2, then they should be able to ping
> each other - the packet flow will be through the DSA switch without
> involving th
On Sun, Jul 12, 2020 at 01:00:48PM +, Martin Rowe wrote:
> On Sat, 11 Jul 2020 at 19:23, Russell King - ARM Linux admin
> wrote:
> > On Sat, Jul 11, 2020 at 06:23:49PM +0200, Andrew Lunn wrote:
> > > So i'm guessing it is the connection between the CPU and the switch.
> > > Could you confirm t
On Sat, 11 Jul 2020 at 19:23, Russell King - ARM Linux admin
wrote:
> On Sat, Jul 11, 2020 at 06:23:49PM +0200, Andrew Lunn wrote:
> > So i'm guessing it is the connection between the CPU and the switch.
> > Could you confirm this? Create a bridge, add two ports of the switch
> > to the bridge, an
On Sat, Jul 11, 2020 at 06:23:49PM +0200, Andrew Lunn wrote:
> So i'm guessing it is the connection between the CPU and the switch.
> Could you confirm this? Create a bridge, add two ports of the switch
> to the bridge, and then see if packets can pass between switch ports.
>
> If it is the connec
On Sat, Jul 11, 2020 at 01:50:21PM +, Martin Rowe wrote:
> Hello,
>
> I hope this is the right forum.
>
> I have been troubleshooting an issue with my Clearfog GT 8Ks where I
> am unable to tx or rx on the switch interface, which uses the
> mv88e6xxx driver. Based on git bisect, I believe it
Hello,
I hope this is the right forum.
I have been troubleshooting an issue with my Clearfog GT 8Ks where I
am unable to tx or rx on the switch interface, which uses the
mv88e6xxx driver. Based on git bisect, I believe it is related to
commit 34b5e6a33c1a8e466c3a73fd437f66fb16cb83ea from around t
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