On Tue, 22 Dec 2020 18:18:31 +0200 Georgi Djakov wrote:
> On 12/22/20 17:16, Alex Elder wrote:
> > When the core clock rate and interconnect bandwidth specifications
> > were moved into configuration data, a copy/paste bug was introduced,
> > causing the memory interconnect bandwidth to be set thre
On 12/22/20 17:16, Alex Elder wrote:
When the core clock rate and interconnect bandwidth specifications
were moved into configuration data, a copy/paste bug was introduced,
causing the memory interconnect bandwidth to be set three times
rather than enabling the three different interconnects.
Fix
