David Miller wrote:
From: Jeff Garzik <[EMAIL PROTECTED]>
Date: Mon, 08 Oct 2007 10:22:28 -0400
In terms of overall parallelization, both for TX as well as RX, my gut
feeling is that we want to move towards an MSI-X, multi-core friendly
model where packets are LIKELY to be sent and received by
On Mon, 2007-08-10 at 15:33 -0700, David Miller wrote:
> Multiply whatever effect you think you might be able to measure due to
> that on your 2 or 4 way system, and multiple it up to 64 cpus or so
> for machines I am using. This is where machines are going, and is
> going to become the norm.
Ye
> Multiply whatever effect you think you might be able to
> measure due to that on your 2 or 4 way system, and multiple
> it up to 64 cpus or so for machines I am using. This is
> where machines are going, and is going to become the norm.
That along with speeds going to 10 GbE with multiple Tx
From: jamal <[EMAIL PROTECTED]>
Date: Mon, 08 Oct 2007 18:30:18 -0400
> Very quickly there are no more packets for it to dequeue from the
> qdisc or the driver is stoped and it has to get out of there. If you
> dont have any interupt tied to a specific cpu then you can have many
> cpus enter and l
On Mon, 2007-08-10 at 14:11 -0700, David Miller wrote:
> The problem is that the packet schedulers want global guarantees
> on packet ordering, not flow centric ones.
>
> That is the issue Jamal is concerned about.
indeed, thank you for giving it better wording.
> The more I think about it, th
From: Jeff Garzik <[EMAIL PROTECTED]>
Date: Mon, 08 Oct 2007 10:22:28 -0400
> In terms of overall parallelization, both for TX as well as RX, my gut
> feeling is that we want to move towards an MSI-X, multi-core friendly
> model where packets are LIKELY to be sent and received by the same set
>
On Mon, 2007-08-10 at 10:22 -0400, Jeff Garzik wrote:
> Any chance the NIC hardware could provide that guarantee?
If you can get the scheduling/dequeuing to run on one CPU (as we do
today) it should work; alternatively you can totaly bypass the qdisc
subystem and go direct to the hardware for dev
