On Mon, 2006-10-23 at 10:09, Zang Roy-r61911 wrote:
> On Thu, 2006-09-21 at 12:46, Jeff Garzik wrote:
>
> > you should have a chip structure, that contains two structs (one for
> > each interface/port)
> >
> Jeff,
>
> I updated the code according to all your feedback and post it here
>
> http:
On Thu, 2006-09-21 at 12:46, Jeff Garzik wrote:
> you should have a chip structure, that contains two structs (one for
> each interface/port)
>
Jeff,
I updated the code according to all your feedback and post it here
http://www.spinics.net/lists/netdev/msg17120.html
Any comment?
Roy
-
To un
On Thu, 2006-09-21 at 12:46, Jeff Garzik wrote:
> > +
> > +/* Synchronization is needed between the thread and up/down events.
> > + * Note that the PHY is accessed through the same registers for
> both
> > + * interfaces, so this can't be made interface-specific.
> > + */
> > +
> > +static DEFINE_
Zang Roy-r61911 wrote:
Could you interpret the chip structure in more detail?
Need I create two net_device struct for each port?
No. One net_device per port. And one container structure for the
entire device.
Jeff
-
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On Thu, 2006-09-21 at 12:46, Jeff Garzik wrote:
> Zang Roy-r61911 wrote:
> > +struct tsi108_prv_data {
> > + void __iomem *regs;/* Base of normal regs */
> > + void __iomem *phyregs; /* Base of register bank used for PHY
> access */
> > +
> > + int phy;/* Inde
Zang Roy-r61911 wrote:
On Thu, 2006-09-21 at 12:26, Jeff Garzik wrote:
Zang Roy-r61911 wrote:
+#define TSI108_ETH_WRITE_REG(offset, val) \
+ writel(le32_to_cpu(val),data->regs + (offset))
+
+#define TSI108_ETH_READ_REG(offset) \
+ le32_to_cpu(readl(data->regs + (offset)))
+
+#define TSI
On Thu, 2006-09-21 at 12:26, Jeff Garzik wrote:
> Zang Roy-r61911 wrote:
> > +#define TSI108_ETH_WRITE_REG(offset, val) \
> > + writel(le32_to_cpu(val),data->regs + (offset))
> > +
> > +#define TSI108_ETH_READ_REG(offset) \
> > + le32_to_cpu(readl(data->regs + (offset)))
> > +
> > +#define
Zang Roy-r61911 wrote:
+struct tsi108_prv_data {
+ void __iomem *regs;/* Base of normal regs */
+ void __iomem *phyregs; /* Base of register bank used for PHY access */
+
+ int phy;/* Index of PHY for this interface */
+ int irq_num;
+ in
Zang Roy-r61911 wrote:
+#define TSI108_ETH_WRITE_REG(offset, val) \
+ writel(le32_to_cpu(val),data->regs + (offset))
+
+#define TSI108_ETH_READ_REG(offset) \
+ le32_to_cpu(readl(data->regs + (offset)))
+
+#define TSI108_ETH_WRITE_PHYREG(offset, val) \
+ writel(le32_to_cpu(val),
On Tue, 2006-09-19 at 15:39 +0800, Zang Roy-r61911 wrote:
> >
> > > + spin_unlock_irq(&phy_lock);
> > > + msleep(10);
> > > + spin_lock_irq(&phy_lock);
> > > + }
> >
> > hmm some places take phy_lock with disabling interrupts, while others
> > don't. I sort of fear "the o
>
> I have some review comments about your driver; please
> consider them for
> fixing
>
Thanks.
>
> > + spin_unlock_irq(&phy_lock);
> > + msleep(10);
> > + spin_lock_irq(&phy_lock);
> > + }
>
> hmm some places take phy_lock with disabling interrupts, while
On Tue, 2006-09-12 at 22:43, Jeff Garzik wrote:
> Roland Dreier wrote:
> > > +struct tsi108_prv_data {
> > > + volatile u32 regs; /* Base of normal regs */
> > > + volatile u32 phyregs; /* Base of register bank used for PHY
> access */
> >
> > Why volatile? This looks really wrong her
Roland Dreier wrote:
> +struct tsi108_prv_data {
> + volatile u32 regs; /* Base of normal regs */
> + volatile u32 phyregs; /* Base of register bank used for PHY access */
Why volatile? This looks really wrong here.
Indeed.
> + data->regs = (u32)ioremap(einfo->regs, 0x400);/
> +struct tsi108_prv_data {
> +volatile u32 regs; /* Base of normal regs */
> +volatile u32 phyregs; /* Base of register bank used for PHY access */
Why volatile? This looks really wrong here.
> +data->regs = (u32)ioremap(einfo->regs, 0x400); /*FIX ME */
> +data->phy
On Tue, 2006-09-12 at 16:55 +0800, Zang Roy-r61911 wrote:
> The driver for tsi108/9 on chip Ethernet port
Hi,
I have some review comments about your driver; please consider them for
fixing
> +
> +#undef DEBUG
> +#ifdef DEBUG
> +#define DBG(fmt...) do { printk(fmt); } while(0)
> +#else
> +#de
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