On Sun, Nov 15, 2020 at 8:48 AM Andy Duan wrote:
>
> From: Kegl Rohit Sent: Sunday, November 15, 2020 1:37 AM
> > On Sat, Nov 14, 2020 at 2:58 AM Andy Duan wrote:
> > >
> > > From: Kegl Rohit Sent: Friday, November 13, 2020
> > > 8:21 PM
> > > > On Fri, Nov 13, 2020 at 8:33 AM Kegl Rohit wrote
From: Kegl Rohit Sent: Sunday, November 15, 2020 1:37 AM
> On Sat, Nov 14, 2020 at 2:58 AM Andy Duan wrote:
> >
> > From: Kegl Rohit Sent: Friday, November 13, 2020
> > 8:21 PM
> > > On Fri, Nov 13, 2020 at 8:33 AM Kegl Rohit wrote:
> > > >
> > > > > What are the addresses of the ring entries?
On Sat, Nov 14, 2020 at 2:58 AM Andy Duan wrote:
>
> From: Kegl Rohit Sent: Friday, November 13, 2020 8:21 PM
> > On Fri, Nov 13, 2020 at 8:33 AM Kegl Rohit wrote:
> > >
> > > > What are the addresses of the ring entries?
> > > > I bet there is something wrong with the cache coherency and/or
> >
From: Kegl Rohit Sent: Friday, November 13, 2020 8:21 PM
> On Fri, Nov 13, 2020 at 8:33 AM Kegl Rohit wrote:
> >
> > > What are the addresses of the ring entries?
> > > I bet there is something wrong with the cache coherency and/or
> > > flushing.
> > >
> > > So the MAC hardware has done the writ
On Fri, Nov 13, 2020 at 8:33 AM Kegl Rohit wrote:
>
> > What are the addresses of the ring entries?
> > I bet there is something wrong with the cache coherency and/or
> > flushing.
> >
> > So the MAC hardware has done the write but (somewhere) it
> > isn't visible to the cpu for ages.
>
> CMA memo
> What are the addresses of the ring entries?
> I bet there is something wrong with the cache coherency and/or
> flushing.
>
> So the MAC hardware has done the write but (somewhere) it
> isn't visible to the cpu for ages.
CMA memory is disabled in our kernel config.
So the descriptors allocated wi
On Thu, Nov 12, 2020 at 2:29 AM Andy Duan wrote:
>
> From: Kegl Rohit Sent: Wednesday, November 11, 2020
> 10:27 PM
> > Hello!
> >
> > We are using a imx6q platform.
> > The fec interface is used to receive a continuous stream of custom / raw
> > ethernet packets. The packet size is fixed ~132 b
From: Kegl Rohit Sent: Wednesday, November 11, 2020 10:27
PM
> Hello!
>
> We are using a imx6q platform.
> The fec interface is used to receive a continuous stream of custom / raw
> ethernet packets. The packet size is fixed ~132 bytes and they get sent every
> 250µs.
>
> While testing I observ
On Wed, Nov 11, 2020 at 6:52 PM David Laight wrote:
>
> > On 11/11/20 3:27 PM, Kegl Rohit wrote:
> > > Hello!
> > >
> > > We are using a imx6q platform.
> > > The fec interface is used to receive a continuous stream of custom /
> > > raw ethernet packets. The packet size is fixed ~132 bytes and th
Hi David,
On Wed, Nov 11, 2020 at 2:52 PM David Laight wrote:
> I've seen a 'fec' ethernet block in a freescale DSP.
> IIRC it is a fairly simple block - won't be doing out-of-order writes.
>
> The imx6q seems to be arm based.
This is correct.
> I'm guessing that means it doesn't do cache cohe
> On 11/11/20 3:27 PM, Kegl Rohit wrote:
> > Hello!
> >
> > We are using a imx6q platform.
> > The fec interface is used to receive a continuous stream of custom /
> > raw ethernet packets. The packet size is fixed ~132 bytes and they get
> > sent every 250µs.
> >
> > While testing I observed spont
On 11/11/20 3:27 PM, Kegl Rohit wrote:
> Hello!
>
> We are using a imx6q platform.
> The fec interface is used to receive a continuous stream of custom /
> raw ethernet packets. The packet size is fixed ~132 bytes and they get
> sent every 250µs.
>
> While testing I observed spontaneous packet
Hello!
We are using a imx6q platform.
The fec interface is used to receive a continuous stream of custom /
raw ethernet packets. The packet size is fixed ~132 bytes and they get
sent every 250µs.
While testing I observed spontaneous packet delays from time to time.
After digging down deeper I thi
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