On Mon, Feb 6, 2017 at 3:50 PM, David Laight wrote:
> From: Saeed Mahameed
>> Sent: 05 February 2017 11:24
>> On Thu, Feb 2, 2017 at 4:47 PM, Daniel Jurgens wrote:
>> > On 2/1/2017 5:12 AM, David Laight wrote:
>> >> From: Saeed Mahameed
>> >>> Sent: 31 January 2017 20:59
>> >>> From: Daniel Jurge
From: Saeed Mahameed
> Sent: 05 February 2017 11:24
> On Thu, Feb 2, 2017 at 4:47 PM, Daniel Jurgens wrote:
> > On 2/1/2017 5:12 AM, David Laight wrote:
> >> From: Saeed Mahameed
> >>> Sent: 31 January 2017 20:59
> >>> From: Daniel Jurgens
> >>>
> >>> There is a hardware feature that will pad th
On Thu, Feb 2, 2017 at 4:47 PM, Daniel Jurgens wrote:
> On 2/1/2017 5:12 AM, David Laight wrote:
>> From: Saeed Mahameed
>>> Sent: 31 January 2017 20:59
>>> From: Daniel Jurgens
>>>
>>> There is a hardware feature that will pad the start or end of a DMA to
>>> be cache line aligned to avoid RMWs
On 2/1/2017 5:12 AM, David Laight wrote:
> From: Saeed Mahameed
>> Sent: 31 January 2017 20:59
>> From: Daniel Jurgens
>>
>> There is a hardware feature that will pad the start or end of a DMA to
>> be cache line aligned to avoid RMWs on the last cache line. The default
>> cache line size setting
From: Saeed Mahameed
> Sent: 31 January 2017 20:59
> From: Daniel Jurgens
>
> There is a hardware feature that will pad the start or end of a DMA to
> be cache line aligned to avoid RMWs on the last cache line. The default
> cache line size setting for this feature is 64B. This change configures
From: Daniel Jurgens
There is a hardware feature that will pad the start or end of a DMA to
be cache line aligned to avoid RMWs on the last cache line. The default
cache line size setting for this feature is 64B. This change configures
the hardware to use 128B alignment on systems with 128B cache
