Re: [TG3 2/3]: Exit irq handler during chip reset.

From: "Michael Chan" <[EMAIL PROTECTED]> Date: Fri, 23 Mar 2007 16:13:07 -0800 > [TG3]: Exit irq handler during chip reset. > > On most tg3 chips, the memory enable bit in the PCI command register > gets cleared during chip reset and must be restored before accessing > PCI registers using memory

[TG3 2/3]: Exit irq handler during chip reset.

[TG3]: Exit irq handler during chip reset. On most tg3 chips, the memory enable bit in the PCI command register gets cleared during chip reset and must be restored before accessing PCI registers using memory cycles. The chip does not generate interrupt during chip reset, but the irq handler can s