On 11/23/2016 05:48 AM, Ido Schimmel wrote:
> Hi Florian,
>
> On Tue, Nov 22, 2016 at 09:56:30AM -0800, Florian Fainelli wrote:
>> On 11/22/2016 09:41 AM, Ido Schimmel wrote:
>>> Hi Florian,
>>>
>>> On Mon, Nov 21, 2016 at 11:09:22AM -0800, Florian Fainelli wrote:
Hi all,
This patch
Hi Florian,
On Tue, Nov 22, 2016 at 09:56:30AM -0800, Florian Fainelli wrote:
> On 11/22/2016 09:41 AM, Ido Schimmel wrote:
> > Hi Florian,
> >
> > On Mon, Nov 21, 2016 at 11:09:22AM -0800, Florian Fainelli wrote:
> >> Hi all,
> >>
> >> This patch series allows using the bridge master interface t
Wed, Nov 23, 2016 at 01:24:30AM CET, f.faine...@gmail.com wrote:
>On 11/22/2016 02:08 PM, Jiri Pirko wrote:
>> Tue, Nov 22, 2016 at 06:48:29PM CET, and...@lunn.ch wrote:
>>> Hi Ido
>>>
First of all, I want to be sure that when we say "CPU port", we're
talking about the same thing. In mlxs
On 11/22/2016 02:08 PM, Jiri Pirko wrote:
> Tue, Nov 22, 2016 at 06:48:29PM CET, and...@lunn.ch wrote:
>> Hi Ido
>>
>>> First of all, I want to be sure that when we say "CPU port", we're
>>> talking about the same thing. In mlxsw, the CPU port is a pipe between
>>> the device and the host, through
Tue, Nov 22, 2016 at 06:48:29PM CET, and...@lunn.ch wrote:
>Hi Ido
>
>> First of all, I want to be sure that when we say "CPU port", we're
>> talking about the same thing. In mlxsw, the CPU port is a pipe between
>> the device and the host, through which all packets trapped to the host
>> go throu
On 11/22/2016 09:41 AM, Ido Schimmel wrote:
> Hi Florian,
>
> On Mon, Nov 21, 2016 at 11:09:22AM -0800, Florian Fainelli wrote:
>> Hi all,
>>
>> This patch series allows using the bridge master interface to configure
>> an Ethernet switch port's CPU/management port with different VLAN attributes
Hi Florian,
On Mon, Nov 21, 2016 at 11:09:22AM -0800, Florian Fainelli wrote:
> Hi all,
>
> This patch series allows using the bridge master interface to configure
> an Ethernet switch port's CPU/management port with different VLAN attributes
> than
> those of the bridge downstream ports/members
Hi Ido
> First of all, I want to be sure that when we say "CPU port", we're
> talking about the same thing. In mlxsw, the CPU port is a pipe between
> the device and the host, through which all packets trapped to the host
> go through. So, when a packet is trapped, the driver reads its Rx
> descr
Hi Florian,
Florian Fainelli writes:
> This patch series allows using the bridge master interface to configure
> an Ethernet switch port's CPU/management port with different VLAN attributes
> than
> those of the bridge downstream ports/members.
>
> Jiri, Ido, Andrew, Vivien, please review the i
Mon, Nov 21, 2016 at 08:09:22PM CET, f.faine...@gmail.com wrote:
>Hi all,
>
>This patch series allows using the bridge master interface to configure
>an Ethernet switch port's CPU/management port with different VLAN attributes
>than
>those of the bridge downstream ports/members.
>
>Jiri, Ido, Andr
Hi all,
This patch series allows using the bridge master interface to configure
an Ethernet switch port's CPU/management port with different VLAN attributes
than
those of the bridge downstream ports/members.
Jiri, Ido, Andrew, Vivien, please review the impact on mlxsw and mv88e6xxx, I
tested thi
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