Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-22 Thread Kurt Kanzenbach
On Mon Jun 22 2020, Andrew Lunn wrote: > On Mon, Jun 22, 2020 at 02:32:28PM +0200, Kurt Kanzenbach wrote: >> On Fri Jun 19 2020, Andrew Lunn wrote: >> >> > Are trace registers counters? >> >> >> >> No. The trace registers provide bits for error conditions and if packets >> >> have been dropped e.g

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-22 Thread Kurt Kanzenbach
Hi Vladimir, On Mon Jun 22 2020, Vladimir Oltean wrote: > Hi Kurt, > > On Mon, 22 Jun 2020 at 15:34, Kurt Kanzenbach wrote: >> >> * Re-prioritization of packets based on the ether type (not mac address) > > This can be done by offloading a tc skbedit priority action, and a > "protocol" key (even

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-22 Thread Vladimir Oltean
Hi Kurt, On Mon, 22 Jun 2020 at 15:34, Kurt Kanzenbach wrote: > > * Re-prioritization of packets based on the ether type (not mac address) This can be done by offloading a tc skbedit priority action, and a "protocol" key (even though I don't understand why you need to mention "not mac address".

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-22 Thread Andrew Lunn
On Mon, Jun 22, 2020 at 02:32:28PM +0200, Kurt Kanzenbach wrote: > On Fri Jun 19 2020, Andrew Lunn wrote: > >> > Are trace registers counters? > >> > >> No. The trace registers provide bits for error conditions and if packets > >> have been dropped e.g. because of full queues or FCS errors, and so

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-22 Thread Kurt Kanzenbach
On Fri Jun 19 2020, Andrew Lunn wrote: >> > Are trace registers counters? >> >> No. The trace registers provide bits for error conditions and if packets >> have been dropped e.g. because of full queues or FCS errors, and so on. > > Is there some documentation somewhere? A better understanding of w

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-19 Thread Andrew Lunn
> > Are trace registers counters? > > No. The trace registers provide bits for error conditions and if packets > have been dropped e.g. because of full queues or FCS errors, and so on. Is there some documentation somewhere? A better understanding of what they can do might help figure out the corr

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-19 Thread Kurt Kanzenbach
Hi Andrew, On Thu Jun 18 2020, Andrew Lunn wrote: > On Thu, Jun 18, 2020 at 08:40:26AM +0200, Kurt Kanzenbach wrote: >> The switch has registers which are useful for debugging issues: > > debugfs is not particularly likes. Please try to find other means > where possible. Memory usage fits nicely i

Re: [RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-18 Thread Andrew Lunn
On Thu, Jun 18, 2020 at 08:40:26AM +0200, Kurt Kanzenbach wrote: > The switch has registers which are useful for debugging issues: debugfs is not particularly likes. Please try to find other means where possible. Memory usage fits nicely into devlink. See mv88e6xxx which exports the ATU fill for e

[RFC PATCH 6/9] net: dsa: hellcreek: Add debugging mechanisms

2020-06-17 Thread Kurt Kanzenbach
The switch has registers which are useful for debugging issues: * Trace registers This can be helpful to trace why packets have been filtered or dropped or if there any other serious problems. * Memory registers These registers provide the current switch internal RAM utilization.