On Fri, Dec 02, 2016 at 02:41:08PM -0500, Vivien Didelot wrote:
> Hi Andrew,
>
> Andrew Lunn writes:
>
> > @@ -3749,6 +3756,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[]
> > = {
> > .global1_addr = 0x1b,
> > .age_time_coeff = 15000,
> > .g1_irqs =
Hi Andrew,
Andrew Lunn writes:
> @@ -3749,6 +3756,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .global1_addr = 0x1b,
> .age_time_coeff = 15000,
> .g1_irqs = 9,
> + .tag_protocol = DSA_TAG_PROTO_EDSA,
> .flags
Older chips support a single tagging protocol, DSA. New chips support
both DSA and EDSA, an enhanced version. Having both as an option
changes the register layouts. Up until now, it has been assumed that
if EDSA is supported, it will be used. Hence the register layout has
been determined by which p
