On 3/23/2018 2:31 PM, Alexander Duyck wrote:
>> Please point me to the redundant ones.
> So from what I can tell only this file and i40e needed any additional
> mmiowb calls added. The rest are not needed.
Thanks, I'll clean up between 2..6 and then make your suggested changes
on 1 and 7.
--
S
On Fri, Mar 23, 2018 at 11:27 AM, Sinan Kaya wrote:
> On 3/23/2018 2:25 PM, Alexander Duyck wrote:
>>> + /* We need this if more than one processor can write to our
>>> tail
>>> +* at a time, it synchronizes IO on IA64/Altix systems
>>> +*/
>>> +
On 3/23/2018 2:25 PM, Alexander Duyck wrote:
>> + /* We need this if more than one processor can write to our
>> tail
>> +* at a time, it synchronizes IO on IA64/Altix systems
>> +*/
>> + mmiowb();
>> }
> The mmiowb shouldn't be n
On Fri, Mar 23, 2018 at 11:21 AM, Sinan Kaya wrote:
> Code includes wmb() followed by writel() in multiple places. writel()
> already has a barrier on some architectures like arm64.
>
> This ends up CPU observing two barriers back to back before executing the
> register write.
>
> Since code alrea
Code includes wmb() followed by writel() in multiple places. writel()
already has a barrier on some architectures like arm64.
This ends up CPU observing two barriers back to back before executing the
register write.
Since code already has an explicit barrier call, changing writel() to
writel_rela
