Hi Andrew,
Andrew Lunn writes:
>> +struct mv88e6xxx_smi_ops {
>> +int (*read)(struct mii_bus *bus, int sw_addr,
>> +int addr, int reg, u16 *val);
>> +int (*write)(struct mii_bus *bus, int sw_addr,
>> + int addr, int reg, u16 val);
>> +};
>
> Hi Vivien
>
>
> +struct mv88e6xxx_smi_ops {
> + int (*read)(struct mii_bus *bus, int sw_addr,
> + int addr, int reg, u16 *val);
> + int (*write)(struct mii_bus *bus, int sw_addr,
> + int addr, int reg, u16 val);
> +};
Hi Vivien
I still think this API should be based on
When the SMI address of the switch chip is zero, the chip assumes to be
the only one on the SMI master bus and thus responds to all its known
SMI devices addresses (port registers, Global2, etc.)
When its SMI address is not zero, some chips (e.g. 88E6352) use an
indirect access through two SMI Com
