Hi Andrew,
Andrew Lunn writes:
>> +struct mv88e6xxx_smi_ops {
>> +int (*read)(struct mii_bus *bus, int sw_addr,
>> +int addr, int reg, u16 *val);
>> +int (*write)(struct mii_bus *bus, int sw_addr,
>> + int addr, int reg, u16 val);
>> +};
>> +
>
> I think t
> +struct mv88e6xxx_smi_ops {
> + int (*read)(struct mii_bus *bus, int sw_addr,
> + int addr, int reg, u16 *val);
> + int (*write)(struct mii_bus *bus, int sw_addr,
> + int addr, int reg, u16 val);
> +};
> +
I think this API would be better if it used ps, n
The Marvell switch models have different mode the access the internal
SMI registers. When the chip address on the SMI master bus is 0, the
chips respond to all SMI devices addresses known to them. When the chip
address is not zero, most chips use an indirect access to registers
using two SMI Comman
