Re: [PATCH v2 net-next 4/8] net: mvneta: sync dma buffers before refilling hw queues

2019-10-10 Thread Lorenzo Bianconi
> On Thu, 10 Oct 2019 01:18:34 +0200 > Lorenzo Bianconi wrote: > > > mvneta driver can run on not cache coherent devices so it is > > necessary to sync dma buffers before sending them to the device > > in order to avoid memory corruption. This patch introduce a performance > > penalty and it is n

Re: [PATCH v2 net-next 4/8] net: mvneta: sync dma buffers before refilling hw queues

2019-10-10 Thread Lorenzo Bianconi
> Hi Lorenzo, Jesper, > > On Thu, Oct 10, 2019 at 09:08:31AM +0200, Jesper Dangaard Brouer wrote: > > On Thu, 10 Oct 2019 01:18:34 +0200 > > Lorenzo Bianconi wrote: > > > > > mvneta driver can run on not cache coherent devices so it is > > > necessary to sync dma buffers before sending them to t

Re: [PATCH v2 net-next 4/8] net: mvneta: sync dma buffers before refilling hw queues

2019-10-10 Thread Ilias Apalodimas
Hi Lorenzo, Jesper, On Thu, Oct 10, 2019 at 09:08:31AM +0200, Jesper Dangaard Brouer wrote: > On Thu, 10 Oct 2019 01:18:34 +0200 > Lorenzo Bianconi wrote: > > > mvneta driver can run on not cache coherent devices so it is > > necessary to sync dma buffers before sending them to the device > > in

Re: [PATCH v2 net-next 4/8] net: mvneta: sync dma buffers before refilling hw queues

2019-10-10 Thread Jesper Dangaard Brouer
On Thu, 10 Oct 2019 01:18:34 +0200 Lorenzo Bianconi wrote: > mvneta driver can run on not cache coherent devices so it is > necessary to sync dma buffers before sending them to the device > in order to avoid memory corruption. This patch introduce a performance > penalty and it is necessary to in

[PATCH v2 net-next 4/8] net: mvneta: sync dma buffers before refilling hw queues

2019-10-09 Thread Lorenzo Bianconi
mvneta driver can run on not cache coherent devices so it is necessary to sync dma buffers before sending them to the device in order to avoid memory corruption. This patch introduce a performance penalty and it is necessary to introduce a more sophisticated logic in order to avoid dma sync as much