On 12/09/2019, David Miller wrote:
> From: Vladimir Oltean
> Date: Thu, 12 Sep 2019 11:17:11 +0100
>
>> Hi Dave,
>>
>> On 12/09/2019, David Miller wrote:
>>> From: Vladimir Oltean
>>> Date: Tue, 10 Sep 2019 04:34:57 +0300
>>>
static int sja1105_ptp_adjfine(struct ptp_clock_info *ptp, long
From: Vladimir Oltean
Date: Thu, 12 Sep 2019 11:17:11 +0100
> Hi Dave,
>
> On 12/09/2019, David Miller wrote:
>> From: Vladimir Oltean
>> Date: Tue, 10 Sep 2019 04:34:57 +0300
>>
>>> static int sja1105_ptp_adjfine(struct ptp_clock_info *ptp, long
>>> scaled_ppm)
>>> {
>>> struct sja1105_
Hi Dave,
On 12/09/2019, David Miller wrote:
> From: Vladimir Oltean
> Date: Tue, 10 Sep 2019 04:34:57 +0300
>
>> static int sja1105_ptp_adjfine(struct ptp_clock_info *ptp, long
>> scaled_ppm)
>> {
>> struct sja1105_private *priv = ptp_to_sja1105(ptp);
>> +const struct sja1105_regs *re
From: Vladimir Oltean
Date: Tue, 10 Sep 2019 04:34:57 +0300
> static int sja1105_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
> {
> struct sja1105_private *priv = ptp_to_sja1105(ptp);
> + const struct sja1105_regs *regs = priv->info->regs;
> s64 clkrate;
> + int
Adjusting the hardware clock (PTPCLKVAL, PTPCLKADD, PTPCLKRATE) is a
requirement for the auxiliary PTP functionality of the switch
(TTEthernet, PPS input, PPS output).
Now that the sync precision issues have been identified (and fixed in
the spi-fsl-dspi driver), we can get rid of the timecounter/
