> On Mon, Feb 06, 2017 at 10:41:44AM +, Mintz, Yuval wrote:
> > Richard - we're planning on sending v4 with the existing algorithm
> > [but without iterating on 'val == 0']; If you have any suggestion for
> > improving this, please share it.
>
> Sorry, haven't had the time to look at your issu
On Mon, Feb 06, 2017 at 10:41:44AM +, Mintz, Yuval wrote:
> Richard - we're planning on sending v4 with the existing algorithm
> [but without iterating on 'val == 0']; If you have any suggestion for
> improving this, please share it.
Sorry, haven't had the time to look at your issue.
BTW, you
> > > + for (val = 0; val <= 7; val++) {
> > > + period1 = div_s64(val * 10, ppb);
> > > + period1 -= 8;
> > > + period1 >>= 4;
> > > + if (period1 < 1)
> > > + period1 = 1;
> > > +
> > + for (val = 0; val <= 7; val++) {
> > + period1 = div_s64(val * 10, ppb);
> > + period1 -= 8;
> > + period1 >>= 4;
> > + if (period1 < 1)
> > + period1 = 1;
> > +
(adding tglx on CC)
On Mon, Jan 30, 2017 at 11:47:48PM -0800, Sudarsana Kalluru wrote:
> +/* Adjust the HW clock by a rate given in parts-per-million (ppm) units.
> + * FW/HW accepts the adjustment value in terms of 3 parameters:
> + * Drift period - adjustment happens once in certain number of
> From: Sudarsana Reddy Kalluru
>
> The patch adds the required qed interfaces for configuring/reading the PTP
> clock on the adapter.
>
> Reviewed-by: Richard Cochran
This Reviewd-by Tag is incorrect; Should have been a CC.
Sorry about that.
> Signed-off-by: Sudarsana Reddy Kalluru
> Signed
From: Sudarsana Reddy Kalluru
The patch adds the required qed interfaces for configuring/reading
the PTP clock on the adapter.
Reviewed-by: Richard Cochran
Signed-off-by: Sudarsana Reddy Kalluru
Signed-off-by: Yuval Mintz
---
drivers/net/ethernet/qlogic/qed/Makefile | 2 +-
drivers/n
