> +/* Offset 0x1D: Misc Register */
> +
> +static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
> + bool port_5_bit)
> +{
> + u16 val;
> + int err;
> +
> + err = mv88e6xxx_g2_read(chip, GLOBAL2_MISC, &val);
> + if (err)
> +
The Cross-chip Port Based VLAN Table (PVT) supports two indexing modes,
one using 5-bit for device and 4-bit for port, the other using 4-bit for
device and 5-bit for port, configured via the Global 2 Misc register.
Only 4 bits for the source port are needed when interconnecting 88E6xxx
switch devi
