Re: [PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register

2017-09-18 Thread David Miller
From: Fahad Kunnathadi Date: Fri, 15 Sep 2017 12:01:58 +0530 > To clear Speed Selection in MDIO control register(0x10), > ie, clear bits 6 and 13 to zero while keeping other bits same. > Before AND operation,The Mask value has to be perform with bitwise NOT > operation (ie, ~ operator) > > This

[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register

2017-09-14 Thread Fahad Kunnathadi
To clear Speed Selection in MDIO control register(0x10), ie, clear bits 6 and 13 to zero while keeping other bits same. Before AND operation,The Mask value has to be perform with bitwise NOT operation (ie, ~ operator) This patch clears current speed selection before writing the new speed settings