On Tue, Feb 14, 2017 at 02:31:53PM +, Claudiu Manoil wrote:
> >-Original Message-
> >From: Andrew Lunn [mailto:and...@lunn.ch]
> >Sent: Monday, February 13, 2017 7:31 PM
> >Subject: Re: [PATCH net] at803x: insure minimum delay for SGMII lin
>-Original Message-
>From: Andrew Lunn [mailto:and...@lunn.ch]
>Sent: Monday, February 13, 2017 7:31 PM
>Subject: Re: [PATCH net] at803x: insure minimum delay for SGMII link AN
>completion ckeck
>
[...]
>>
>> I can confirm that link status chang
> Yes, the phy is operating in interrupt mode.
> The phy nodes from the board's device tree have their interrupt properties
> set:
> http://lxr.free-electrons.com/source/arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts
>
> I can confirm that link status changes are signaled via interrupts
> ("phy_inter
Fainelli
>> Subject: Re: [PATCH net] at803x: insure minimum delay for SGMII link AN
>> completion ckeck
>>
>> On 02/10/2017 05:42 PM, Claudiu Manoil wrote:
>>> Commit: f62265b "at803x: double check SGMII side autoneg"
>>> introduced a regressio
>-Original Message-
>From: Zefir Kurtisi [mailto:zefir.kurt...@neratec.com]
>Sent: Monday, February 13, 2017 12:16 PM
>To: Claudiu Manoil
>Cc: netdev@vger.kernel.org; David S. Miller ; Florian
>Fainelli
>Subject: Re: [PATCH net] at803x: insure minimum delay for SGMI
On 02/10/2017 05:42 PM, Claudiu Manoil wrote:
> Commit: f62265b "at803x: double check SGMII side autoneg"
> introduced a regression for the p1010rdb board which has
> two of the ethernet controllers (eTSEC) connected through
> SGMII links to external Atheros SGMII AR8033 PHYs.
> The issue consists
On 02/10/2017 08:42 AM, Claudiu Manoil wrote:
> Commit: f62265b "at803x: double check SGMII side autoneg"
> introduced a regression for the p1010rdb board which has
> two of the ethernet controllers (eTSEC) connected through
> SGMII links to external Atheros SGMII AR8033 PHYs.
> The issue consists
Commit: f62265b "at803x: double check SGMII side autoneg"
introduced a regression for the p1010rdb board which has
two of the ethernet controllers (eTSEC) connected through
SGMII links to external Atheros SGMII AR8033 PHYs.
The issue consists in a dead link for these ports, and is
100% reproducible
