On Wed, Mar 31, 2021 at 5:28 PM Will Deacon wrote:
>
> On Wed, Mar 31, 2021 at 05:22:18PM +0800, Jianlin Lv wrote:
> > On Tue, Mar 30, 2021 at 5:31 PM Will Deacon wrote:
> > >
> > > On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote:
> > > > A64_MOV is currently mapped to Add Instruction.
On Wed, Mar 31, 2021 at 05:22:18PM +0800, Jianlin Lv wrote:
> On Tue, Mar 30, 2021 at 5:31 PM Will Deacon wrote:
> >
> > On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote:
> > > A64_MOV is currently mapped to Add Instruction. Architecturally MOV
> > > (register) is an alias of ORR (shifte
On Tue, Mar 30, 2021 at 5:31 PM Will Deacon wrote:
>
> On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote:
> > A64_MOV is currently mapped to Add Instruction. Architecturally MOV
> > (register) is an alias of ORR (shifted register) and MOV (to or from SP)
> > is an alias of ADD (immediate)
On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote:
> A64_MOV is currently mapped to Add Instruction. Architecturally MOV
> (register) is an alias of ORR (shifted register) and MOV (to or from SP)
> is an alias of ADD (immediate).
> This patch redefines A64_MOV and uses existing functionali
A64_MOV is currently mapped to Add Instruction. Architecturally MOV
(register) is an alias of ORR (shifted register) and MOV (to or from SP)
is an alias of ADD (immediate).
This patch redefines A64_MOV and uses existing functionality
aarch64_insn_gen_move_reg() in insn.c to encode MOV (register) in
