> At the moment I use this driver with a KSZ8795CLX, port 5 directly
> connected to a MACB/GEM of a Zynq SOC, with the need to enable the
> RGMII internal clock delay (register 0x56, bit 4), otherwise the
> the Zynq cannot talk to the switch on its RGMII interface
Hi Helmut
This is possible with
On 02/08/2016 05:38 AM, Florian Fainelli wrote:
On 07/02/2016 14:39, Helmut Buchsbaum wrote:
Since several use cases need to setup at least some basic control
registers add the ability to configure an array containing such
register initialization values within the platform data of the switch.
Fu
On 07/02/2016 14:39, Helmut Buchsbaum wrote:
> Since several use cases need to setup at least some basic control
> registers add the ability to configure an array containing such
> register initialization values within the platform data of the switch.
> Furthermore expose this capabilty to the devi
Since several use cases need to setup at least some basic control
registers add the ability to configure an array containing such
register initialization values within the platform data of the switch.
Furthermore expose this capabilty to the devicetree.
Platform data now contains a pointer to an a
