On Fri, Jul 28, 2017 at 03:07:03PM -0700, Alexandru Gagniuc wrote:
> Before the GMAC on the Anarion chip can be used, the PHY interface
> selection must be configured with the DWMAC block in reset.
>
> This layer covers a block containing only two registers. Although it
> is possible to model this
On Mon, Jul 31, 2017 at 08:11:00AM -0700, Alex wrote:
> Hi David,
>
> On 07/28/2017 07:01 PM, David Miller wrote:
> > From: Alexandru Gagniuc
> > Date: Fri, 28 Jul 2017 15:07:03 -0700
> >
> > > Before the GMAC on the Anarion chip can be used, the PHY interface
> > > selection must be configured
Hi David,
On 07/28/2017 07:01 PM, David Miller wrote:
From: Alexandru Gagniuc
Date: Fri, 28 Jul 2017 15:07:03 -0700
Before the GMAC on the Anarion chip can be used, the PHY interface
selection must be configured with the DWMAC block in reset.
This layer covers a block containing only two reg
From: Alexandru Gagniuc
Date: Fri, 28 Jul 2017 15:07:03 -0700
> Before the GMAC on the Anarion chip can be used, the PHY interface
> selection must be configured with the DWMAC block in reset.
>
> This layer covers a block containing only two registers. Although it
> is possible to model this as
Before the GMAC on the Anarion chip can be used, the PHY interface
selection must be configured with the DWMAC block in reset.
This layer covers a block containing only two registers. Although it
is possible to model this as a reset controller and use the "resets"
property of stmmac, it's much mor
