On Mon, 07 Dec 2020 10:31:46 +0100 Jerome Brunet wrote:
> > The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
> > shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
> > struct clk_mux expects the mask relative to the "shift" field in the
> > same struct.
> >
On Sat 05 Dec 2020 at 22:32, Martin Blumenstingl
wrote:
> The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
> shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
> struct clk_mux expects the mask relative to the "shift" field in the
> same struct.
>
> Whi
The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
struct clk_mux expects the mask relative to the "shift" field in the
same struct.
While here, get rid of the PRG_ETH0_CLK_M250_SEL_SHIFT macro and use
__ffs(
