Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

2019-02-04 Thread Andrew Lunn
On Mon, Feb 04, 2019 at 04:38:53PM -0500, John David Anglin wrote: > On 2019-02-04 3:19 p.m., Andrew Lunn wrote: > > The IRQ core would do this if it was needed. > > > > How many other irq thread work functions can you point to which do > > something similar? > This is comment for handle_edge_irq:

Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

2019-02-04 Thread John David Anglin
On 2019-02-04 3:19 p.m., Andrew Lunn wrote: > The IRQ core would do this if it was needed. > > How many other irq thread work functions can you point to which do > something similar? This is comment for handle_edge_irq: /**  *    handle_edge_irq - edge type IRQ handler  *    @desc:    the interrup

Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

2019-02-04 Thread Andrew Lunn
> Can you be more specific regarding what you think is wrong with this hunk? Hi David The IRQ core would do this if it was needed. How many other irq thread work functions can you point to which do something similar? Andrew

Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

2019-02-04 Thread John David Anglin
Hi Andrew, On 2019-02-04 2:35 p.m., Andrew Lunn wrote: > The change to the interrupt handler i'm pretty sure is wrong. You have > to accept with edge interrupts you are going to loose interrupts. Can you be more specific regarding what you think is wrong with this hunk? I can see that an interrup

Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

2019-02-04 Thread Andrew Lunn
On Mon, Feb 04, 2019 at 01:37:13PM -0500, John David Anglin wrote: > This change fixes a race condition in the setup of hardware irqs and the > code enabling PHY link > detection. > > This was observed on the espressobin board where the GPIO interrupt > controller only supports edge > interrupts. 

[PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

2019-02-04 Thread John David Anglin
This change fixes a race condition in the setup of hardware irqs and the code enabling PHY link detection. This was observed on the espressobin board where the GPIO interrupt controller only supports edge interrupts.  If the INTn output pin goes low before the GPIO interrupt is enabled, PHY link i