Re: [PATCH] net: dsa: allow XAUI phy interface mode

2017-12-12 Thread Andrew Lunn
> That's something like it - asked Andrew via IRC on Saturday: > > Do we want to do the XAUI thing as one patch to avoid any breakage, and > if so via whom? Hi Russell Sorry for not replying. I was on a plane by then. > and haven't had a response. Normally arm-soc folk want patches > touching

Re: [PATCH] net: dsa: allow XAUI phy interface mode

2017-12-11 Thread Russell King - ARM Linux
On Mon, Dec 11, 2017 at 01:54:03PM -0500, David Miller wrote: > From: Russell King > Date: Fri, 08 Dec 2017 16:04:59 + > > > XGMII is a 32-bit bus plus two clock signals per direction. XAUI is > > four serial lanes per direction. The 88e6190 supports XAUI but not > > XGMII as it doesn't hav

Re: [PATCH] net: dsa: allow XAUI phy interface mode

2017-12-11 Thread David Miller
From: Russell King Date: Fri, 08 Dec 2017 16:04:59 + > XGMII is a 32-bit bus plus two clock signals per direction. XAUI is > four serial lanes per direction. The 88e6190 supports XAUI but not > XGMII as it doesn't have enough pins. The same is true of 88e6176. > > Match on PHY_INTERFACE_M

Re: [PATCH] net: dsa: allow XAUI phy interface mode

2017-12-09 Thread Andrew Lunn
> You do seem to be correct that this only applies (in mainline) to the > ZII rev C board, so I guess including a patch to update its dts for > the inter-switch connection would at least be sensible. Hi Russell So lets have the backward compatible for a couple of kernel cycles, and modify ZII rev

Re: [PATCH] net: dsa: allow XAUI phy interface mode

2017-12-08 Thread Russell King - ARM Linux
On Fri, Dec 08, 2017 at 05:26:43PM +0100, Andrew Lunn wrote: > On Fri, Dec 08, 2017 at 04:04:59PM +, Russell King wrote: > > XGMII is a 32-bit bus plus two clock signals per direction. XAUI is > > four serial lanes per direction. The 88e6190 supports XAUI but not > > XGMII as it doesn't have

Re: [PATCH] net: dsa: allow XAUI phy interface mode

2017-12-08 Thread Andrew Lunn
On Fri, Dec 08, 2017 at 04:04:59PM +, Russell King wrote: > XGMII is a 32-bit bus plus two clock signals per direction. XAUI is > four serial lanes per direction. The 88e6190 supports XAUI but not > XGMII as it doesn't have enough pins. The same is true of 88e6176. > > Match on PHY_INTERFAC

[PATCH] net: dsa: allow XAUI phy interface mode

2017-12-08 Thread Russell King
XGMII is a 32-bit bus plus two clock signals per direction. XAUI is four serial lanes per direction. The 88e6190 supports XAUI but not XGMII as it doesn't have enough pins. The same is true of 88e6176. Match on PHY_INTERFACE_MODE_XAUI for the XAUI port type, but keep accepting XGMII for backwar