On 08/04/17 18:18, Florian Fainelli wrote:
>
>
> On 04/08/2017 08:10 AM, Andrew Lunn wrote:
>> On Sat, Apr 08, 2017 at 06:55:45AM -0700, David Miller wrote:
>>> From: Roger Quadros
>>> Date: Wed, 5 Apr 2017 11:33:57 +0300
>>>
Some boards [1] leave the PHYs at an invalid state
during sy
On 04/08/2017 08:10 AM, Andrew Lunn wrote:
> On Sat, Apr 08, 2017 at 06:55:45AM -0700, David Miller wrote:
>> From: Roger Quadros
>> Date: Wed, 5 Apr 2017 11:33:57 +0300
>>
>>> Some boards [1] leave the PHYs at an invalid state
>>> during system power-up or reset thus causing unreliability
>>> i
On Sat, Apr 08, 2017 at 06:55:45AM -0700, David Miller wrote:
> From: Roger Quadros
> Date: Wed, 5 Apr 2017 11:33:57 +0300
>
> > Some boards [1] leave the PHYs at an invalid state
> > during system power-up or reset thus causing unreliability
> > issues with the PHY like not being detected by the
From: Roger Quadros
Date: Wed, 5 Apr 2017 11:33:57 +0300
> Some boards [1] leave the PHYs at an invalid state
> during system power-up or reset thus causing unreliability
> issues with the PHY like not being detected by the mdio bus
> or link not functional. To work around these boards have
> a G
On 06/04/17 15:05, Andrew Lunn wrote:
>>> Do you really need more than one GPIO? A single gpio would make all
>>> this code a lot simpler.
>>>
>>
>> Yes we need. Some of our boards have separate GPIO RESET lines for
>> different PHYs on the same MDIO bus.
>
> If you have a one-to-one mapping of G
> > Do you really need more than one GPIO? A single gpio would make all
> > this code a lot simpler.
> >
>
> Yes we need. Some of our boards have separate GPIO RESET lines for
> different PHYs on the same MDIO bus.
If you have a one-to-one mapping of GPIO and PHY, you should really be
modelling
Hi,
On 05/04/17 18:03, Andrew Lunn wrote:
> On Wed, Apr 05, 2017 at 11:33:57AM +0300, Roger Quadros wrote:
>> Some boards [1] leave the PHYs at an invalid state
>> during system power-up or reset thus causing unreliability
>> issues with the PHY like not being detected by the mdio bus
>> or link n
On Wed, Apr 05, 2017 at 11:33:57AM +0300, Roger Quadros wrote:
> Some boards [1] leave the PHYs at an invalid state
> during system power-up or reset thus causing unreliability
> issues with the PHY like not being detected by the mdio bus
> or link not functional. To work around these boards have
>
Some boards [1] leave the PHYs at an invalid state
during system power-up or reset thus causing unreliability
issues with the PHY like not being detected by the mdio bus
or link not functional. To work around these boards have
a GPIO connected to the PHY's reset pin.
Implement GPIO reset handling
