Hi Willy
On Wed, 7 Apr 2021 at 17:42, Willy Tarreau wrote:
> > There are two new status bits TBNQ and FBNQ at bits 7 and 8. I have no
> > idea what they mean.
>
> Maybe they're related to tx queue empty / tx queue full. Just guessing.
> Since all these bits tend not to be reset until written to,
Hi,
On 07/04/2021 10:42:07+0200, Willy Tarreau wrote:
> Hi Daniel,
>
> On Tue, Apr 06, 2021 at 07:04:58PM +0900, Daniel Palmer wrote:
> > Hi Willy,
> >
> > I've been messing with the SSD202D (sibling of the MSC313E) recently
> > and the ethernet performance was awful.
> > I remembered this rever
Hi Daniel,
On Tue, Apr 06, 2021 at 07:04:58PM +0900, Daniel Palmer wrote:
> Hi Willy,
>
> I've been messing with the SSD202D (sibling of the MSC313E) recently
> and the ethernet performance was awful.
> I remembered this revert and reverted it and it makes the ethernet
> work pretty well.
OK, th
Hi Willy,
I've been messing with the SSD202D (sibling of the MSC313E) recently
and the ethernet performance was awful.
I remembered this revert and reverted it and it makes the ethernet
work pretty well.
So I would like to find some way of making this patch work and I did
some digging..
On Thu,
From: Willy Tarreau
Date: Wed, 9 Dec 2020 19:47:40 +0100
> This reverts commit 0a4e9ce17ba77847e5a9f87eed3c0ba46e3f82eb.
>
> The code was developed and tested on an MSC313E SoC, which seems to be
> half-way between the AT91RM9200 and the AT91SAM9260 in that it supports
> both the 2-descriptors
This reverts commit 0a4e9ce17ba77847e5a9f87eed3c0ba46e3f82eb.
The code was developed and tested on an MSC313E SoC, which seems to be
half-way between the AT91RM9200 and the AT91SAM9260 in that it supports
both the 2-descriptors mode and a Tx ring.
It turns out that after the code was merged I cou
