On Fri, Sep 08, 2006 at 10:23:36PM +0200, Francois Romieu wrote:
> > I suspect it's a chip bug. I rechecked with I/O space, and that
> > works okay, so this artifact (bug) only manifests itself when you
> > do the upper write in MMIO space.
> >
> > Are there any plans to switch r8169 to the iomap
Lennert Buytenhek <[EMAIL PROTECTED]> :
[...]
> I tried your series from step (1) plus my TxDesc change (so I didn't
> include the hunk from (2)), and that seems to work fine. I.e. I don't
> need to disable error interrupts anymore to keep it working.
>
> So really the only thing that would need
Lennert Buytenhek <[EMAIL PROTECTED]> :
[...]
> I suspect it's a chip bug. I rechecked with I/O space, and that works
> okay, so this artifact (bug) only manifests itself when you do the upper
> write in MMIO space.
>
> Are there any plans to switch r8169 to the iomap API? Would you take
> a patc
On Sun, Aug 20, 2006 at 11:35:58PM +0200, Francois Romieu wrote:
> > 2. SYSErr asserts pretty soon after upping eth0, and the PCI status
> >register reports a parity error when this happens. In this case,
> >the restart logic seems to make things worse, and in fact, when
> >commenting
On Sun, Aug 20, 2006 at 11:35:58PM +0200, Francois Romieu wrote:
> > 1. Writing zero to the upper part of the TxDescStartAddr register (via
> >the MMIO region) somehow also clears the lower part, and writing the
> >upper and lower halves the other way round fixes it. The RxDescAddr
> >
Lennert Buytenhek <[EMAIL PROTECTED]> :
[...]
> The hack patch below makes it work. There's two issues here:
>
> 1. Writing zero to the upper part of the TxDescStartAddr register (via
>the MMIO region) somehow also clears the lower part, and writing the
>upper and lower halves the other w
On Fri, Jul 28, 2006 at 12:11:09PM +0200, Lennert Buytenhek wrote:
> We're currently working on getting the Thecus n2100 supported in 2.6.
>
> http://www.thecus.com/products_over.php?cid=1&pid=1
>
> Amongst other nice goodies, it has two on-board RTL8110SB gigabit
> controllers. The realt
