@vger.kernel.org;
> devicet...@vger.kernel.org; f.faine...@gmail.com; Quette, Arnaud
>
> Subject: Re: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for
> SMSC LAN8720
>
> > > > (ii) This defeats the purpose of a previous commit [2] that
> > > > disabled the ref clo
> > > (ii) This defeats the purpose of a previous commit [2] that disabled
> > > the ref clock for power saving reasons. If a ref clock for the PHY is
> > > specified in DT, the SMSC driver will keep it always on (confirmed
> > > with scope).
> >
> > NACK, the clock provider can be any clock. This
de; lgirdw...@gmail.com;
> broo...@kernel.org; robh...@kernel.org; richard.leit...@skidata.com;
> netdev@vger.kernel.org; devicet...@vger.kernel.org; f.faine...@gmail.com;
> Quette, Arnaud
> Subject: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for SMSC
> LAN8720
>
&g
t; To: Badel, Laurent
> Subject: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for SMSC
> LAN8720
>
> On Tue, 27 Oct 2020 23:25:01 + Badel, Laurent wrote:
> > Subject: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720
> >
> > Description:
>
