From: Thierry Reding
This reverts commit 9c63faaa931e443e7abbbee9de0169f1d4710546, which
introduces a suspend/resume regression on Jetson TX2 boards that can be
reproduced every time. Given that the issue that this was supposed to
fix only occurs very sporadically the safest course of action is
On Wed, Apr 14, 2021 at 02:18:58AM +, Joakim Zhang wrote:
>
> > -Original Message-
> > From: Thierry Reding
> > Sent: 2021年4月14日 0:07
> > To: David S. Miller ; Jakub Kicinski
> > Cc: Joakim Zhang ; Jon Hunter
> > ; Giuseppe Cavallaro ;
> &g
On Tue, Apr 13, 2021 at 12:13:01PM +, Joakim Zhang wrote:
>
> Hi Jon,
>
> > -Original Message-
> > From: Jon Hunter
> > Sent: 2021年4月13日 16:41
> > To: Joakim Zhang ; Giuseppe Cavallaro
> > ; Alexandre Torgue ;
> > Jose Abreu
> > Cc: netdev@vger.kernel.org; Linux Kernel Mailing List
On Mon, Mar 22, 2021 at 01:33:38PM -0700, Dipen Patel wrote:
> Hi Richard,
>
> Thanks for your input and time. Please see below follow up.
>
> On 3/20/21 8:38 AM, Richard Cochran wrote:
> > On Sat, Mar 20, 2021 at 01:44:20PM +0100, Arnd Bergmann wrote:
> >> Adding Richard Cochran as well, for dri
From: Thierry Reding
When dumping the name and NTP servers advertised by DHCP, a blank line
is emitted if either of the lists is empty. This can lead to confusing
issues such as the blank line getting flagged as warning. This happens
because the blank line is the result of pr_cont("\n"
c.yaml | 2 ++
> .../bindings/sound/nvidia,tegra210-i2s.yaml | 2 ++
[...]
> .../bindings/usb/nvidia,tegra-xudc.yaml | 2 ++
[...]
Acked-by: Thierry Reding
signature.asc
Description: PGP signature
On Fri, Aug 07, 2020 at 01:02:44PM +0200, Thierry Reding wrote:
> On Thu, Aug 06, 2020 at 07:09:16PM -0700, John Stultz wrote:
> > On Thu, Aug 6, 2020 at 6:52 AM Thierry Reding
> > wrote:
> > >
> > > On Wed, Apr 22, 2020 at 08:32:43PM +, John Stultz wrot
On Thu, Aug 06, 2020 at 07:09:16PM -0700, John Stultz wrote:
> On Thu, Aug 6, 2020 at 6:52 AM Thierry Reding
> wrote:
> >
> > On Wed, Apr 22, 2020 at 08:32:43PM +, John Stultz wrote:
> > > This patch addresses a regression in 5.7-rc1+
> > >
> > &
From: Thierry Reding
Query the USB device's device tree node when looking for a MAC address.
The struct device embedded into the struct net_device does not have a
device tree node attached at all.
The reason why this went unnoticed is because the system where this was
tested was one of th
ructive. So perhaps we can find
some other way for drivers to advertise that their dependencies are
optional? I came up with the below patch, which restores suspend/resume
on Tegra and could be used in conjunction with a patch that opts into
this behaviour for the problematic driver in Yoshihiro
From: Thierry Reding
If a MAC address was passed via the device tree node for the r8152
device, use it and fall back to reading from EEPROM otherwise. This is
useful for devices where the r8152 EEPROM was not programmed with a
valid MAC address, or if users want to explicitly set a MAC address
From: Thierry Reding
The DWMAC 4.10 supports the same enhanced addressing mode as later
generations. Parse this capability from the hardware feature registers
and set the EAME (Enhanced Addressing Mode Enable) bit when necessary.
Thierry
Thierry Reding (2):
net: stmmac: Only enable enhanced
From: Thierry Reding
The address width of the controller can be read from hardware feature
registers much like on XGMAC. Add support for parsing the ADDR64 field
so that the DMA mask can be set accordingly.
This avoids getting swiotlb involved for DMA on Tegra186 and later.
Also make sure that
From: Thierry Reding
Enhanced addressing mode is only required when more than 32 bits need to
be addressed. Add a DMA configuration parameter to enable this mode only
when needed.
Signed-off-by: Thierry Reding
---
Changes in v4:
- enable EAME only if DMA addresses can be larger than 32 bits
>
> >>> From: Jose Abreu
> >>> Date: Wed, 25 Sep 2019 10:44:53 +
> >>>
> >>>> From: David Miller
> >>>> Date: Sep/24/2019, 20:45:08 (UTC+00:00)
> >>>>
> >>>>> From: Thierry Reding
> >>
On Tue, Sep 24, 2019 at 09:45:08PM +0200, David Miller wrote:
> From: Thierry Reding
> Date: Fri, 20 Sep 2019 19:00:34 +0200
>
> > From: Thierry Reding
> >
> > The DWMAC 4.10 supports the same enhanced addressing mode as later
> > generations. Parse this cap
On Mon, Sep 23, 2019 at 11:59:15AM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> The size of individual pages in the page pool in given by an order. The
> order is the binary logarithm of the number of pages that make up one of
> the pages in the pool. However, the d
From: Thierry Reding
The size of individual pages in the page pool in given by an order. The
order is the binary logarithm of the number of pages that make up one of
the pages in the pool. However, the driver currently passes the number
of pages rather than the order, so it ends up wasting quite
On Fri, Sep 20, 2019 at 10:02:28AM -0700, Florian Fainelli wrote:
> On 9/20/19 10:00 AM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > The DWMAC 4.10 supports the same enhanced addressing mode as later
> > generations. Parse this capability from the hardwar
From: Thierry Reding
Enhanced addressing mode is only required when more than 32 bits need to
be addressed. Add a DMA configuration parameter to enable this mode only
when needed.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 -
drivers/net
From: Thierry Reding
The DWMAC 4.10 supports the same enhanced addressing mode as later
generations. Parse this capability from the hardware feature registers
and set the EAME (Enhanced Addressing Mode Enable) bit when necessary.
Thierry
Thierry Reding (2):
net: stmmac: Only enable enhanced
From: Thierry Reding
The size of individual pages in the page pool in given by an order. The
order is the binary logarithm of the number of pages that make up one of
the pages in the pool. However, the driver currently passes the number
of pages rather than the order, so it ends up wasting quite
From: Thierry Reding
The address width of the controller can be read from hardware feature
registers much like on XGMAC. Add support for parsing the ADDR64 field
so that the DMA mask can be set accordingly.
This avoids getting swiotlb involved for DMA on Tegra186 and later.
Also make sure that
On Tue, Sep 10, 2019 at 08:32:38AM +, Jose Abreu wrote:
> From: Thierry Reding
> Date: Sep/09/2019, 20:11:27 (UTC+00:00)
>
> > On Mon, Sep 09, 2019 at 04:07:04PM +, Jose Abreu wrote:
> > > From: Thierry Reding
> > > Date: Sep/09/2019, 16:25:45 (UTC+00:
On Mon, Sep 09, 2019 at 04:05:52PM +, Jose Abreu wrote:
> From: Thierry Reding
> Date: Sep/09/2019, 16:25:46 (UTC+00:00)
>
> > @@ -79,6 +79,10 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
> > value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
&
On Mon, Sep 09, 2019 at 04:07:04PM +, Jose Abreu wrote:
> From: Thierry Reding
> Date: Sep/09/2019, 16:25:45 (UTC+00:00)
>
> > @@ -92,6 +92,7 @@ struct stmmac_dma_cfg {
> > int fixed_burst;
> > int mixed_burst;
> > bool aal;
> > + bool
From: Thierry Reding
Enhanced addressing mode is only required when more than 32 bits need to
be addressed. Add a DMA configuration parameter to enable this mode only
when needed.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 -
drivers/net
From: Thierry Reding
The address width of the controller can be read from hardware feature
registers much like on XGMAC. Add support for parsing the ADDR64 field
so that the DMA mask can be set accordingly.
This avoids getting swiotlb involved for DMA on Tegra186 and later.
Also make sure that
On Mon, Sep 09, 2019 at 02:36:27PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> The address width of the controller can be read from hardware feature
> registers much like on XGMAC. Add support for parsing the ADDR64 field
> so that the DMA mask can be set accordi
From: Thierry Reding
Enhanced addressing mode is only required when more than 32 bits need to
be addressed. Add a DMA configuration parameter to enable this mode only
when needed.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 -
drivers/net
From: Thierry Reding
The address width of the controller can be read from hardware feature
registers much like on XGMAC. Add support for parsing the ADDR64 field
so that the DMA mask can be set accordingly.
This avoids getting swiotlb involved for DMA on Tegra186 and later.
Also make sure that
From: Thierry Reding
The Tegra EQOS driver already resets the MDIO bus at probe time via the
reset GPIO specified in the phy-reset-gpios device tree property. There
is no need to reset the bus again later on.
This avoids the need to query the device tree for the snps,reset GPIO,
which is not
From: Thierry Reding
The stmmaceth clock is specified by the slave_bus and apb_pclk clocks in
the device tree bindings for snps,dwc-qos-ethernet-4.10 compatible nodes
of this IP.
The subdrivers for these bindings will be requesting the stmmac clock
correctly at a later point, so there is no
From: Thierry Reding
If the subdriver defers probe, do not show an error message. It's
perfectly fine for this error to occur since the driver will get another
chance to probe after some time and will usually succeed after all of
the resources that it requires have been registered.
Signe
On Wed, Feb 06, 2019 at 01:30:18PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> Read MAC address 32-bit at a time and manually extract the individual
> bytes. This avoids pointer aliasing and gives the compiler a better
> chance of optimizing the operation.
>
>
On Wed, Feb 06, 2019 at 01:30:17PM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> If the system was booted using a device tree and if the device tree
> contains a MAC address, use it instead of reading one from the EEPROM.
> This is useful in situations where the EEPROM
From: Thierry Reding
If the system was booted using a device tree and if the device tree
contains a MAC address, use it instead of reading one from the EEPROM.
This is useful in situations where the EEPROM isn't properly programmed
or where the firmware wants to override the existing MAC ad
From: Thierry Reding
Read MAC address 32-bit at a time and manually extract the individual
bytes. This avoids pointer aliasing and gives the compiler a better
chance of optimizing the operation.
Suggested-by: Andrew Lunn
Signed-off-by: Thierry Reding
---
Applies to net-next.
I tested this on
From: Thierry Reding
If the system was booted using a device tree and if the device tree
contains a MAC address, use it instead of reading one from the EEPROM.
This is useful in situations where the EEPROM isn't properly programmed
or where the firmware wants to override the existing MAC ad
From: Thierry Reding
Read MAC address 32-bit at a time and manually extract the individual
bytes. This avoids pointer aliasing and gives the compiler a better
chance of optimizing the operation.
Suggested-by: Andrew Lunn
Signed-off-by: Thierry Reding
---
Applies to net-next.
I tested this on
On Fri, Jan 25, 2019 at 07:34:31PM +0100, Heiner Kallweit wrote:
> On 25.01.2019 11:18, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > If the system was booted using a device tree and if the device tree
> > contains a MAC address, use it instead of reading on
On Fri, Jan 25, 2019 at 03:57:11PM +0100, Andrew Lunn wrote:
> On Fri, Jan 25, 2019 at 11:18:14AM +0100, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > If the system was booted using a device tree and if the device tree
> > contains a MAC address, use it inst
From: Thierry Reding
If the system was booted using a device tree and if the device tree
contains a MAC address, use it instead of reading one from the EEPROM.
This is useful in situations where the EEPROM isn't properly programmed
or where the firmware wants to override the existing MAC ad
On Wed, Nov 28, 2018 at 09:38:32AM +, Jose Abreu wrote:
> On 27-11-2018 13:21, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Setting up and tearing down debugfs is current unbalanced, as seen by
> > this error during resume from suspend:
> >
>
On Tue, Nov 27, 2018 at 09:02:51AM +, Jose Abreu wrote:
> On 26-11-2018 15:34, Thierry Reding wrote:
> > On Fri, Nov 23, 2018 at 12:44:02PM +, Jose Abreu wrote:
> >> On 23-11-2018 12:21, Thierry Reding wrote:
> >>> From: Thierry Reding
> >>>
&g
From: Thierry Reding
Setting up and tearing down debugfs is current unbalanced, as seen by
this error during resume from suspend:
[ 752.134067] dwc-eth-dwmac 249.ethernet eth0: ERROR failed to create
debugfs directory
[ 752.134347] dwc-eth-dwmac 249.ethernet eth0
On Fri, Nov 23, 2018 at 12:44:02PM +, Jose Abreu wrote:
> On 23-11-2018 12:21, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Setting up and tearing down debugfs is current unbalanced, as seen by
> > this error during resume from suspend:
> >
>
On Fri, Nov 23, 2018 at 12:44:02PM +, Jose Abreu wrote:
> On 23-11-2018 12:21, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Setting up and tearing down debugfs is current unbalanced, as seen by
> > this error during resume from suspend:
> >
>
From: Thierry Reding
Setting up and tearing down debugfs is current unbalanced, as seen by
this error during resume from suspend:
[ 752.134067] dwc-eth-dwmac 249.ethernet eth0: ERROR failed to create
debugfs directory
[ 752.134347] dwc-eth-dwmac 249.ethernet eth0
From: Thierry Reding
Some drivers, such as DWC EQOS on Tegra, need to perform operations that
can sleep under this lock (clk_set_rate() in tegra_eqos_fix_speed()) for
proper operation. Since there is no need for this lock to be a spinlock,
convert it to a mutex instead.
Fixes: e6ea2d16fc61
From: Thierry Reding
Currently the certs C code generation appends to the generated files,
which is most likely a leftover from commit 715a12334764 ("wireless:
don't write C files on failures"). This causes duplicate code in the
generated files if the certificates have their time
On Thu, Aug 17, 2017 at 08:40:16PM +0800, Ding Tianhong wrote:
>
>
> On 2017/8/17 18:51, Thierry Reding wrote:
> > On Thu, Aug 17, 2017 at 10:25:30AM +0800, Ding Tianhong wrote:
> >> The pci_find_pcie_root_port() would return NULL if the given
> >> dev is a
From: Thierry Reding
If the pci_find_pcie_root_port() function is called on a root port
itself, return the root port rather than NULL.
This effectively reverts commit 0e405232871d6 ("PCI: fix oops when
try to find Root Port for a PCI device") which added an extra check
that wo
v under this circumstances.
>
> Fixes: 0e405232871d6 ("PCI: fix oops when try to find Root Port for a PCI
> device")
> Suggested-by: Thierry Reding
> Suggested-by: Bjorn Helgaas
> Signed-off-by: Thierry Reding
> Signed-off-by: Ding Tianhong
> ---
> drivers/pci/
On Tue, Aug 15, 2017 at 12:03:31PM -0500, Bjorn Helgaas wrote:
> On Tue, Aug 15, 2017 at 11:24:48PM +0800, Ding Tianhong wrote:
> > Eric report a oops when booting the system after applying
> > the commit a99b646afa8a ("PCI: Disable PCIe Relaxed..."):
> > ...
>
> > It looks like the pci_find_pcie_
On Thu, Jun 08, 2017 at 03:25:26PM +0200, Christoph Hellwig wrote:
> DMA_ERROR_CODE is not supposed to be used by drivers.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/firmware/tegra/ivc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-
On Thu, Apr 06, 2017 at 09:49:09AM +0100, Joao Pinto wrote:
[...]
> err_init_rx_buffers:
> - while (--i >= 0)
> - stmmac_free_rx_buffer(priv, i);
> + while (queue >= 0) {
I /think/ this could simply be:
while (queue--) {
...
}
That evaluates b
_to_use; queue++) {
> + struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
> +
> + netif_napi_add(ndev, &rx_q->napi, stmmac_poll,
> +(8 * priv->plat->rx_queues_to_use));
> + }
Why is this moving to ->probe() now?
This works on Tegra186, so:
Reviewed-by: Thierry Reding
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On Tue, Apr 04, 2017 at 06:54:25PM +0100, Joao Pinto wrote:
[...]
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
[...]
> @@ -3402,6 +3474,9 @@ static irqreturn_t stmmac_interrupt(int irq, void
> *dev_id)
>
> i
+-
> drivers/net/ethernet/stmicro/stmmac/ring_mode.c | 46 +-
> drivers/net/ethernet/stmicro/stmmac/stmmac.h | 26 +-
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 521
> +-
> 4 files changed, 375 insertions(+), 256 deletions(-)
Looks good to me:
One more nit: subject should say "... for RX" for consistency with patch
3/4.
Thierry
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p to
~0 and probably crash stmmac_free_rx_buffers().
Other than that, this looks fine, so with the above fixed:
Reviewed-by: Thierry Reding
Also works on Tegra186, so:
Tested-by: Thierry Reding
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e
it doesn't provide any useful information, so might as well drop it.
> + if (ret)
> + return ret;
> +
> + /* TX INITIALIZATION */
> + ret = init_dma_tx_desc_rings(dev);
Same here.
[...]
> -static void free_dma_desc_resources(struct stmmac_priv *priv)
> +/**
> + * alloc_dma_desc_resources - alloc TX/RX resources.
> + * @priv: private structure
> + * Description: according to which descriptor can be used (extend or basic)
> + * this function allocates the resources for TX and RX paths. In case of
> + * reception, for example, it pre-allocated the RX socket buffer in order to
> + * allow zero-copy mechanism.
> + */
> +static int alloc_dma_desc_resources(struct stmmac_priv *priv)
> +{
> + /* RX Allocation */
> + int ret = alloc_dma_rx_desc_resources(priv);
And here.
> +
> + if (ret)
> + return ret;
> +
> + /* TX Allocation */
> + ret = alloc_dma_tx_desc_resources(priv);
And here.
None of the above comments are critical and this could be cleaned up in
follow-up patches, so:
Reviewed-by: Thierry Reding
It also doesn't break on Tegra186, so
Tested-by: Thierry Reding
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On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote:
> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote:
> > From: Arnd Bergmann
> > Date: Tue, 28 Mar 2017 11:48:21 +0200
> >
> > > A driver must not access the two fields directly but should instead use
> > > the helper func
On Tue, Mar 28, 2017 at 04:10:43PM +0200, Niklas Cassel wrote:
>
>
> On 03/28/2017 03:57 PM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Even if hardware supports multiple queues, software can choose to only
> > use a subset of them. Make sure we
On Tue, Mar 28, 2017 at 03:34:58PM +0200, Niklas Cassel wrote:
>
>
> On 03/27/2017 07:44 PM, Joao Pinto wrote:
> > Às 6:28 PM de 3/27/2017, David Miller escreveu:
> >> From: Corentin Labbe
> >> Date: Mon, 27 Mar 2017 19:00:58 +0200
> >>
> >>> On Mon, Mar 27, 2017 at 04:26:48PM +0100, Joao Pinto
From: Thierry Reding
Even if hardware supports multiple queues, software can choose to only
use a subset of them. Make sure we never try to access uninitialized
queues.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
1 file changed, 1 insertion
From: Thierry Reding
Some of the data in the new queue structures seems to not be properly
initialized, causing undefined behaviour (networking will work about 2
out of 10 tries). kcalloc() will zero the allocated memory and results
in 10 out of 10 successful boots.
Signed-off-by: Thierry
From: Thierry Reding
Taking the address of an element within a non-NULL array will never be
zero. This condition isn't checked anywhere else, so drop it in these
two instances as well.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 --
1
On Thu, Mar 23, 2017 at 05:27:08PM +, Joao Pinto wrote:
> Hi Thierry,
>
> Às 5:17 PM de 3/23/2017, Thierry Reding escreveu:
> > On Fri, Mar 17, 2017 at 04:11:05PM +, Joao Pinto wrote:
> >> This patch creates 2 new structures (stmmac_tx_queue and stmmac_rx_queu
On Fri, Mar 17, 2017 at 04:11:05PM +, Joao Pinto wrote:
> This patch creates 2 new structures (stmmac_tx_queue and stmmac_rx_queue)
> in include/linux/stmmac.h, enabling that each RX and TX queue has its
> own buffers and data.
>
> Signed-off-by: Joao Pinto
> ---
> changes v1->v2:
> - just to
t; 1 file changed, 3 insertions(+), 3 deletions(-)
With Florian's comments addressed, this is:
Reviewed-by: Thierry Reding
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Florian's comments addressed, this is:
Reviewed-by: Thierry Reding
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On Tue, Mar 21, 2017 at 03:23:00PM +, Joao Pinto wrote:
> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu:
> > From: Thierry Reding
> >
> > Prior to the recent multi-queue changes the driver would configure the
> > queues to use the AVB mode, but the mode th
On Tue, Mar 21, 2017 at 03:18:20PM +, Joao Pinto wrote:
> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu:
> > From: Thierry Reding
> >
> > The MAC RX queues always need to be enabled in order to receive network
> > packets. Remove the condition that this only
From: Thierry Reding
Recent changes to support multiple queues in the device tree bindings
resulted in the number of RX and TX queues to be initialized to zero for
device trees not adhering to the new bindings.
Restore backwards-compatibility with those device trees by falling back
to a single
From: Thierry Reding
The MAC RX queues always need to be enabled in order to receive network
packets. Remove the condition that this only needs to be done for multi-
queue configurations.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
1 file
From: Thierry Reding
Prior to the recent multi-queue changes the driver would configure the
queues to use the AVB mode, but the mode then got switched to DCB. The
hardware still works fine in DCB mode, but my testing capabilities are
limited, so it's safer to revert to the prior setting a
On Tue, Mar 21, 2017 at 02:25:15PM +, Joao Pinto wrote:
> Às 2:23 PM de 3/21/2017, Corentin Labbe escreveu:
> > On Tue, Mar 21, 2017 at 02:10:47PM +, Joao Pinto wrote:
> >> ++Adding Corentin
> >>
> >> Às 2:08 PM de 3/21/2017, Thierry Reding escreveu:
On Tue, Mar 21, 2017 at 02:18:59PM +, Joao Pinto wrote:
> Às 2:08 PM de 3/21/2017, Thierry Reding escreveu:
> > On Tue, Mar 21, 2017 at 01:58:36PM +, Joao Pinto wrote:
> >> Às 12:24 PM de 3/21/2017, Thierry Reding escreveu:
> >>> On Tue, Mar 21, 2017 at 12:0
On Tue, Mar 21, 2017 at 01:58:36PM +, Joao Pinto wrote:
> Às 12:24 PM de 3/21/2017, Thierry Reding escreveu:
> > On Tue, Mar 21, 2017 at 12:02:03PM +, Joao Pinto wrote:
> >> Às 11:58 AM de 3/21/2017, Thierry Reding escreveu:
> >>> On Fri, Mar 10, 2017 at 06:2
On Tue, Mar 21, 2017 at 12:02:03PM +, Joao Pinto wrote:
> Às 11:58 AM de 3/21/2017, Thierry Reding escreveu:
> > On Fri, Mar 10, 2017 at 06:24:52PM +, Joao Pinto wrote:
> >> This patch adds the RX and TX scheduling algorithms programming.
> >> It int
On Tue, Mar 21, 2017 at 11:39:24AM +, Joao Pinto wrote:
>
> Hi Thierry,
>
> Às 11:32 AM de 3/21/2017, Thierry Reding escreveu:
> > On Fri, Mar 10, 2017 at 06:24:51PM +, Joao Pinto wrote:
> >> This patch adds the multiple queues configuration in the Device Tree.
On Fri, Mar 10, 2017 at 06:24:52PM +, Joao Pinto wrote:
> This patch adds the RX and TX scheduling algorithms programming.
> It introduces the multiple queues configuration function
> (stmmac_mtl_configuration) in stmmac_main.
>
> Signed-off-by: Joao Pinto
> ---
> Changes v4->v5:
> - patch ti
On Fri, Mar 10, 2017 at 06:24:51PM +, Joao Pinto wrote:
> This patch adds the multiple queues configuration in the Device Tree.
> It was also created a set of structures to keep the RX and TX queues
> configurations to be used in the driver.
>
> Signed-off-by: Joao Pinto
> ---
> Changes v4->v
sertions(+), 2 deletions(-)
Reviewed-by: Thierry Reding
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From: Thierry Reding
New version of this core encode the FIFO sizes in one of the feature
registers. Use these sizes as default, but still allow device tree to
override them for backwards compatibility.
Reviewed-by: Mikko Perttunen
Signed-off-by: Thierry Reding
---
Changes in v2:
- provide
From: Thierry Reding
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP core. The binding that it uses is slightly different
from existing ones because of the integration (clocks, resets, ...).
Signed-off-by: Thierry Reding
---
Changes in v2:
- use
From: Thierry Reding
There aren't currently any users of the "clk_ptp_ref", but there are
other references to "ptp_ref", so I'm leaning towards considering that a
typo. Fix it.
Cc: Mark Rutland
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Thie
From: Thierry Reding
Program the receive queue size based on the RX FIFO size and enable
hardware flow control for large FIFOs.
Signed-off-by: Thierry Reding
---
Changes in v2:
- add comments to clarify flow control threshold programming
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 12
From: Thierry Reding
Split out the binding specific parts of ->probe() and ->remove() to
enable the driver to support variants of the binding. This is useful in
order to keep backwards-compatibility while making it easy for a sub-
driver to deal only with the updated bindings rather than
From: Thierry Reding
If an error occurs while opening the device, make sure to disable the
PTP reference clock.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac
From: Thierry Reding
Hi everyone,
This series of patches start with a few cleanups that I ran across while
adding Tegra186 support to the stmmac driver. It then adds code for FIFO
size parsing from feature registers and finally enables support for the
incarnation of the Synopsys DWC QOS IP
From: Thierry Reding
If an error occurs while opening the device, make sure that both the TX
timer and the PHY are properly cleaned up.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a
From: Thierry Reding
clk_prepare_enable() and clk_disable_unprepare() for this clock aren't
properly balanced, which can trigger a WARN_ON() in the common clock
framework.
Reviewed-By: Joao Pinto
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
From: Thierry Reding
When DMA mapping an SKB fragment, the mapping must be checked for
errors, otherwise the DMA debug code will complain upon unmap.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a
On Thu, Mar 09, 2017 at 01:18:11PM -0700, Stephen Warren wrote:
> On 03/09/2017 12:42 PM, Thierry Reding wrote:
> > On Mon, Feb 27, 2017 at 12:09:02PM +0200, Mikko Perttunen wrote:
> > > On 23.02.2017 19:24, Thierry Reding wrote:
> > > > From: Thierry Reding
> &
On Mon, Feb 27, 2017 at 01:46:01PM +0200, Mikko Perttunen wrote:
> On 23.02.2017 19:24, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
> > ethernet QOS IP core. The binding that it uses is
On Thu, Mar 02, 2017 at 03:15:12PM +, Joao Pinto wrote:
> Às 5:24 PM de 2/23/2017, Thierry Reding escreveu:
> > From: Thierry Reding
> >
> > Program the receive queue size based on the RX FIFO size and enable
> > hardware flow control for large FIFOs.
> >
On Mon, Feb 27, 2017 at 12:09:02PM +0200, Mikko Perttunen wrote:
> On 23.02.2017 19:24, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Program the receive queue size based on the RX FIFO size and enable
> > hardware flow control for large FIFOs.
> >
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