From: Stephen Warren
This patch solves a crash at the time of mlx4 driver unload or system
shutdown. The crash occurs because dma_alloc_coherent() returns one
value in mlx4_alloc_icm_coherent(), but a different value is passed to
dma_free_coherent() in mlx4_free_icm_coherent(). In turn this is
From: Stephen Warren
pci_{,un}map_sg are deprecated and replaced by dma_{,un}map_sg. This is
especially relevant since the rest of the driver uses the DMA API. Fix
the driver to use the replacement APIs.
Signed-off-by: Stephen Warren
---
v4: New patch.
---
drivers/net/ethernet/mellanox/mlx4
On 12/20/18 10:43 AM, Jason Gunthorpe wrote:
On Wed, Dec 19, 2018 at 11:20:31AM -0700, Stephen Warren wrote:
From: Stephen Warren
This patch solves a crash at the time of mlx4 driver unload or system
shutdown. The crash occurs because dma_alloc_coherent() returns one
value in
From: Stephen Warren
This patch solves a crash at the time of mlx4 driver unload or system
shutdown. The crash occurs because dma_alloc_coherent() returns one
value in mlx4_alloc_icm_coherent(), but a different value is passed to
dma_free_coherent() in mlx4_free_icm_coherent(). In turn this is
On 12/19/18 12:25 AM, Christoph Hellwig wrote:
On Tue, Dec 18, 2018 at 05:12:41PM -0700, Stephen Warren wrote:
On 12/18/18 1:56 PM, Christoph Hellwig wrote:
This goes in the right direction, but I think we need to stop
abusing the scatterlist for the coherent mapping entirely. Something
like
On 12/18/18 1:56 PM, Christoph Hellwig wrote:
This goes in the right direction, but I think we need to stop
abusing the scatterlist for the coherent mapping entirely. Something
like the patch below (based on yours):
Oh, it was simple to get rid of the sg list usage than I thought; I'd
assume
From: Stephen Warren
This patch solves a crash at the time of mlx4 driver unload or system
shutdown. The crash occurs because dma_alloc_coherent() returns one
value in mlx4_alloc_icm_coherent(), but a different value is passed to
dma_free_coherent() in mlx4_free_icm_coherent(). In turn this is
On 12/18/18 10:12 AM, Jason Gunthorpe wrote:
On Tue, Dec 18, 2018 at 10:08:56AM -0700, Stephen Warren wrote:
On 12/18/18 9:32 AM, Jason Gunthorpe wrote:
On Fri, Dec 14, 2018 at 04:32:54PM -0700, Stephen Warren wrote:
From: Stephen Warren
This is a port of commit 378efe798ecf ("RDMA/hns
On 12/18/18 9:32 AM, Jason Gunthorpe wrote:
On Fri, Dec 14, 2018 at 04:32:54PM -0700, Stephen Warren wrote:
From: Stephen Warren
This is a port of commit 378efe798ecf ("RDMA/hns: Get rid of page
operation after dma_alloc_coherent") to the mlx4 driver. That change was
describe
From: Stephen Warren
This is a port of commit 378efe798ecf ("RDMA/hns: Get rid of page
operation after dma_alloc_coherent") to the mlx4 driver. That change was
described as:
> In general, dma_alloc_coherent() returns a CPU virtual address and
> a DMA address, and we have no gu
On 03/09/2017 12:42 PM, Thierry Reding wrote:
On Mon, Feb 27, 2017 at 12:09:02PM +0200, Mikko Perttunen wrote:
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
Program the receive queue size based on the RX FIFO size and enable
hardware flow control for large FIFOs.
diff --g
Niklas Cassel wrote at Monday, December 12, 2016 9:25 AM:
...
> However, I've noticed that NVIDIA has extended the DWC EQoS DT binding,
> I don't how easy it would be for them to switch to stmmac's DT binding.
> (Adding Stephen Warren to CC.)
I don't believe there&
On 09/01/2016 01:02 PM, Stephen Warren wrote:
From: Stephen Warren
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding to define a "compatible value" for the configuration
On 09/01/2016 01:50 AM, Lars Persson wrote:
On 08/31/2016 11:48 PM, Stephen Warren wrote:
On 08/31/2016 03:15 AM, Lars Persson wrote:
On 08/30/2016 10:50 PM, Stephen Warren wrote:
On 08/30/2016 01:01 PM, Rob Herring wrote:
On Wed, Aug 24, 2016 at 03:20:46PM -0600, Stephen Warren wrote
From: Stephen Warren
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding to define a "compatible value" for the configuration
contained in NVIDIA's Tegra186 SoC, and
On 08/31/2016 03:15 AM, Lars Persson wrote:
On 08/30/2016 10:50 PM, Stephen Warren wrote:
On 08/30/2016 01:01 PM, Rob Herring wrote:
On Wed, Aug 24, 2016 at 03:20:46PM -0600, Stephen Warren wrote:
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type
On 08/30/2016 01:01 PM, Rob Herring wrote:
On Wed, Aug 24, 2016 at 03:20:46PM -0600, Stephen Warren wrote:
From: Stephen Warren
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding
From: Stephen Warren
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding to define a "compatible value" for the configuration
contained in NVIDIA's Tegra186 SoC, and
On 08/24/2016 02:10 AM, Lars Persson wrote:
On 08/23/2016 10:47 PM, Stephen Warren wrote:
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding to define a "compatible value&quo
From: Stephen Warren
The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding to define a "compatible value" for the configuration
contained in NVIDIA's Tegra186 SoC, and
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