Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Acked-by: Rob Herring
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 25 ++-
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Robert Hancock
Changed since v1:
-Clarified clock usages in documentation and code comments
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 25 ++
drivers/net/ethernet/xilinx
On Wed, 2021-03-24 at 11:08 -0600, Rob Herring wrote:
> On Fri, Mar 12, 2021 at 01:52:13PM -0600, Robert Hancock wrote:
> > Update DT bindings to describe all of the clocks that the axienet
> > driver will now be able to make use of.
> >
> > Si
On Sun, 2021-03-14 at 14:27 -0700, David Miller wrote:
> From: Robert Hancock
> Date: Thu, 11 Mar 2021 14:11:15 -0600
>
> > Add support to the axienet driver for controlling all of the clocks that
> > the logic core may utilize.
>
> This series does not apply
On Sat, 2021-03-13 at 02:45 +0100, Andrew Lunn wrote:
> On Thu, Mar 11, 2021 at 02:18:13PM -0600, Robert Hancock wrote:
> > When using a fixed-link configuration in SGMII mode, it's not really
> > sensible to have auto-negotiation enabled since the link settings are
> &g
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Robert Hancock
Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 25 ++-
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation
nged since v1:
-Clarified clock usages in documentation and code comments
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 25 ++
drivers/net/ethernet/xilinx/xilinx
On Fri, 2021-03-12 at 18:39 +, Radhey Shyam Pandey wrote:
> > -Original Message-
> > From: Robert Hancock
> > Sent: Friday, March 12, 2021 11:13 PM
> > To: Radhey Shyam Pandey ; da...@davemloft.net;
> > k...@kernel.org
> > Cc: netdev@vger.kernel.org
Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 25 ++-
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation
e comments
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 25 ++
drivers/net/ethernet/xilinx/xilinx_axienet.h | 8 +++--
.../net/ethernet/xilinx/xilinx_axienet_m
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Robert Hancock
On Thu, 2021-03-11 at 14:11 -0600, Robert Hancock wrote:
> This driver was only enabling the first clock on the device, regardless
> of its name. However, this controller logic can have multiple clocks
> which should all be enabled. Add support for enabling additional clocks.
> The
Some fixes to the macb driver for use in SGMII mode with a fixed-link (such as
for chip-to-chip connectivity).
Robert Hancock (2):
net: macb: poll for fixed link state in SGMII mode
net: macb: Disable PCS auto-negotiation for SGMII fixed-link mode
drivers/net/ethernet/cadence/macb.h
When using a fixed-link configuration in SGMII mode, it's not really
sensible to have auto-negotiation enabled since the link settings are
fixed by definition. In other configurations, such as an SGMII
connection to a PHY, it should generally be enabled.
Signed-off-by: Robert Ha
link state is actually up.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/cadence/macb_main.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 15362d016a87..ca72a16c8da3 100644
--- a
well as the Xilinx device tree generator, except for mgt_clk
which is not present there.
For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx
Update DT bindings to describe all of the clocks that the axienet
driver will now be able to make use of.
Signed-off-by: Robert Hancock
---
.../bindings/net/xilinx_axienet.txt | 23 ++-
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/Documentation
Add support to the axienet driver for controlling all of the clocks that
the logic core may utilize.
Robert Hancock (2):
dt-bindings: net: xilinx_axienet: Document additional clocks
net: axienet: Enable more clocks
.../bindings/net/xilinx_axienet.txt | 23 +
drivers
The driver did not always clean up all allocated resources when probe
failed. Fix the probe cleanup path to clean up everything that was
allocated.
Fixes: 57baf8cc70 ("net: axienet: Handle deferred probe on clock properly")
Signed-off-by: Robert Hancock
---
.../net/ether
Add a flag and helper function to indicate that a PHY device is part of
an SFP module, which is set on attach. This can be used by PHY drivers
to handle SFP-specific quirks or behavior.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phy_device.c | 2 ++
include/linux/phy.h | 11
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 8e7fc3368380
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
Acked-by: Florian Fainelli
---
drivers/net/phy/broadcom.c | 84 --
include/linux/brcmphy.h
indentation
-Added missing setting of MII_BCM54XX_AUXCTL_MISC_WREN in
MII_BCM54XX_AUXCTL_SHDWSEL_MISC register
Robert Hancock (3):
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for
BCM54616S
net: phy: Add is_on_sfp_module flag and phy_on_sfp helper
net: phy: broadcom: Do not
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 8e7fc3368380
Add a flag and helper function to indicate that a PHY device is part of
an SFP module, which is set on attach. This can be used by PHY drivers
to handle SFP-specific quirks or behavior.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phy_device.c | 2 ++
include/linux/phy.h | 11
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
Acked-by: Florian Fainelli
---
drivers/net/phy/broadcom.c | 84 --
include/linux/brcmphy.h
MII_BCM54XX_AUXCTL_MISC_WREN in
MII_BCM54XX_AUXCTL_SHDWSEL_MISC register
Robert Hancock (3):
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for
BCM54616S
net: phy: Add is_on_sfp_module flag and phy_on_sfp helper
net: phy: broadcom: Do not modify LED configuration for SFP module
interface.
Signed-off-by: Robert Hancock
---
Changed since v1: Fixed typo and added more explanation in commit message
drivers/net/phy/marvell.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index
On Sat, 2021-02-13 at 10:45 +, Russell King - ARM Linux admin wrote:
> On Fri, Feb 12, 2021 at 08:18:40PM -0600, Robert Hancock wrote:
> > + if (!phydev->sfp_bus &&
> > + (!phydev->attached_dev || !phydev->attached_dev->sfp_bus)) {
>
> First
On Sat, 2021-02-13 at 17:43 +0100, Andrew Lunn wrote:
> On Fri, Feb 12, 2021 at 06:23:56PM -0600, Robert Hancock wrote:
> > Newer versions of the Xilinx AXI Ethernet core (specifically version 7.2 or
> > later) allow the core to be configured with a PHY interface mode of "B
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 484791ac236b
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 84 --
include/linux/brcmphy.h| 4 ++
2 files changed
Updates to the Broadcom PHY driver related to use with copper SFP modules.
Changed since v1:
-Reversed conditional to reduce indentation
-Added missing setting of MII_BCM54XX_AUXCTL_MISC_WREN in
MII_BCM54XX_AUXCTL_SHDWSEL_MISC register
Robert Hancock (2):
net: phy: broadcom: Set proper
On Fri, 2021-02-12 at 17:26 -0800, Florian Fainelli wrote:
>
> On 2/12/2021 4:28 PM, 'Robert Hancock' via BCM-KERNEL-FEEDBACK-LIST,PDL
> wrote:
> > The default configuration for the BCM54616S PHY may not match the desired
> > mode when using 1000BaseX or SGMII inte
On Sat, 2021-02-13 at 01:09 +, Russell King - ARM Linux admin wrote:
> On Fri, Feb 12, 2021 at 06:26:29PM -0600, Robert Hancock wrote:
> > When 88E111 is operating in SGMII mode, auto-negotiation should be enabled
>
> 88E.
yup..
>
> > on the SGMII side so th
some
other mode like 1000BaseX, as may happen in some SFP module situations,
it may not be.
Call genphy_check_and_restart_aneg on the fiber page to ensure that auto-
negotiation is properly enabled on the SGMII interface.
Signed-off-by: Robert Hancock
---
drivers/net/phy/marvell.c | 13
Document the new xlnx,switch-x-sgmii attribute which is used to indicate
that the Ethernet core supports dynamic switching between 1000BaseX and
SGMII.
Signed-off-by: Robert Hancock
---
Documentation/devicetree/bindings/net/xilinx_axienet.txt | 4
1 file changed, 4 insertions(+)
diff
Hook up the nway_reset ethtool operation to the corresponding phylink
function so that "ethtool -r" can be supported.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ether
Updates to the Broadcom PHY driver related to use with copper SFP modules.
Robert Hancock (2):
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for
BCM54616S
net: phy: broadcom: Do not modify LED configuration for SFP module
PHYs
drivers/net/phy/broadcom.c | 109
plications
which can use both fiber and copper SFP modules.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 29 +
.../net/ethernet/xilinx/xilinx_axienet_main.c | 60 ---
2 files changed, 71 insertions(+), 18 deletions(-)
diff --git a/d
. Skip this configuration for PHYs which are bound to an SFP
bus.
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 78542580f2b2
/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock
---
drivers/net/phy/broadcom.c | 83 --
include/linux/brcmphy.h| 4 ++
2 files changed
using an MDIO
bus, as the clock is required in any case.
Fixes: 09a0354cadec267be7f ("net: axienet: Use clock framework to get device
clock rate")
Signed-off-by: Robert Hancock
---
.../net/ethernet/xilinx/xilinx_axienet_main.c | 26 +--
1 file changed, 12 inserti
Updates to the Xilinx AXI Ethernet driver to add support for an additional
ethtool operation, and to support dynamic switching between 1000BaseX and
SGMII interface modes.
Robert Hancock (3):
net: axienet: hook up nway_reset ethtool operation
dt-bindings: net: xilinx_axienet: add xlnx,switch
Add maintainers entry for the Qualcomm QCA807x PHY driver.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 667d03852191..48f32ef108d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14775,6
IPQ40xx, IPQ60xx and IPQ807x
boards.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
Changes in v2:
* Drop LED related code
* Fix ordering in KConfig and Makefile
* Add SFP module validation upon instert
* Rework IRQ code
* Convert values for PSGMII/QSGMII SerDes driver
into register values
Add DT bindings for Qualcomm QCA807x PHYs.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
Changes in v2:
* Drop LED properties
* Directly define PSGMII/QSGMII SerDes driver values
.../devicetree/bindings/net/qcom,qca807x.yaml | 70 +++
1 file changed, 70 insertions(+)
create
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
Changes in v2:
* Drop PSGMII/QSGMII TX driver defines
include/dt-bindings/net/qcom-qca807x.h | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 include/dt
to driver generic LED-s controlled by
user space, so lets enable registering each PHY as GPIO controller and
add driver for it.
Robert Marko (4):
dt-bindings: net: Add QCA807x PHY
dt-bindings: net: Add bindings for Qualcomm QCA807x
net: phy: Add Qualcomm QCA807x driver
MAINTAINERS: Add
Figured I would poke someone to add this patch to the stable queue - I
don't see it in
https://patchwork.kernel.org/bundle/netdev/stable/?state=* right now.
This patch is reported to fix a severe upload speed regression in many
Intel wireless adapters existing since kernel 5.9, as described in
http
uosl.org
>> Cc: dos...@vmware.com ; jesse.brandeb...@intel.com
>> ; anthony.l.ngu...@intel.com
>> ; Morbitzer, Mathias
>> ; Robert Buhren
>> ; f...@sect.tu-berlin.de
>> ; Banse, Christian
>> ; brijesh.si...@amd.com
>> ; thomas.lenda...@amd.com ;
>&g
On Sun, Jan 3, 2021 at 6:00 PM Andrew Lunn wrote:
>
> > > > + qcom,tx-driver-strength:
> > > > +description: PSGMII/QSGMII TX driver strength control.
> > > > +$ref: /schemas/types.yaml#/definitions/uint32
> > > > +enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]
> > >
> > > Please us
On Wed, Dec 23, 2020 at 1:56 AM Andrew Lunn wrote:
>
> > + gpio-controller: true
> > + "#gpio-cells":
> > +const: 2
> > +
> > + qcom,single-led-1000:
> > +description: |
> > + If present, then dedicated 1000 Mbit will light up for 1000Base-T.
> > + This is a workround for boar
Add maintainers entry for the Qualcomm QCA807x PHY driver.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 281de213ef47..a86731f86292 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14546,6
Add DT bindings for Qualcomm QCA807x PHYs.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
.../devicetree/bindings/net/qcom,qca807x.yaml | 88 +++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/qcom,qca807x.yaml
diff --git a
IPQ40xx, IPQ60xx and IPQ807x
boards.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
drivers/net/phy/Kconfig | 10 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/qca807x.c | 811 ++
3 files changed, 822 insertions(+)
create mode 100644 drivers/net/phy
to driver generic LED-s controlled by
user space, so lets enable registering each PHY as GPIO controller and
add driver for it.
Robert Marko (4):
dt-bindings: net: Add QCA807x PHY
dt-bindings: net: Add bindings for Qualcomm QCA807x
net: phy: Add Qualcomm QCA807x driver
MAINTAINERS: Add
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
include/dt-bindings/net/qcom-qca807x.h | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/net/qcom-qca807x.h
diff --git a/include/dt-bindings
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
Reviewed-by: Russell King
---
Changed since v4: Fixed coding style in m88e_config_init_1000basex.
drivers/net/phy/marvell.c | 100 +++-
include
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
Changed since v2
On Tue, 2020-10-27 at 14:25 +, Radhey Shyam Pandey wrote:
> > -Original Message-
> > From: Robert Hancock
> > Sent: Tuesday, October 27, 2020 1:15 AM
> > To: Radhey Shyam Pandey ; da...@davemloft.net;
> > k...@kernel.org
> > Cc: li...@armlin
On Mon, 2020-10-26 at 18:57 +, Radhey Shyam Pandey wrote:
> Thanks for the patch.
>
> > -Original Message-
> > From: Robert Hancock
> > Sent: Monday, October 26, 2020 11:26 PM
> > To: Radhey Shyam Pandey ; da...@davemloft.net;
> > k...@
The Xilinx PCS/PMA PHY requires that BMCR_ISOLATE be disabled for proper
operation in 1000BaseX mode. It should be safe to ensure this bit is
disabled in phylink_mii_c22_pcs_config in all cases.
Signed-off-by: Robert Hancock
Reviewed-by: Russell King
---
Resubmit tagged for net-next.
drivers
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
Reviewed-by: Russell King
---
Changed in v4: Fixed variable order in m88e_config_aneg, added Russell's
Reviewed-by
drivers/net/phy/marvell.c
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
Resubmit of v2 tagged
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
---
Changed since v2: Renamed 1000BX -> 1000X to avoid confusion with 1000Base-BX
drivers/net/phy/marvell.c | 99 -
include/linux/marvell_ph
The Xilinx PCS/PMA PHY requires that BMCR_ISOLATE be disabled for proper
operation in 1000BaseX mode. It should be safe to ensure this bit is
disabled in phylink_mii_c22_pcs_config in all cases.
Signed-off-by: Robert Hancock
---
drivers/net/phy/phylink.c | 3 ++-
1 file changed, 2 insertions
://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert Hancock
---
drivers/net/phy/marvell.c | 99 -
include/linux/marvell_phy.h | 3 ++
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet
to a Linux PC on the other end, but
unfortunately ethtool doesn't seem to report the link partner
advertisements on that adapter, only the host advertisements (Intel
82574L, e1000e).
--
Robert Hancock
Senior Hardware Designer, Advanced Technologies
www.calian.com
estion as I'm not
familiar with all the other setups where this part would be used. So
I'm inclined to leave that part specific to this ID.
--
Robert Hancock
Senior Hardware Designer, Advanced Technologies
www.calian.com
1000BaseT between the module PHY and the
copper link partner. I believe the 88E has some smarts to delay the
copper negotiation until it gets the advertisement over 1000BaseX, uses
those to figure out its advertisement, and then uses the copper link
partner's response to determine the 1000Ba
> + netdev_warn(ndev, "Failed to configure PCS:
> > %d\n",
> > + ret);
> > +
> > + /* Ensure isolate bit is cleared */
> > + ret = mdiobus_modify(lp->pcs_phy->bus, lp->pcs_phy-
> > >addr,
> > +
_MODE_COPPER_1000BX_AN
> > |
> > +MII_M_HWCFG_SERIAL_AN_BYPASS);
> > + if (err < 0)
> > + return err;
> > + }
> > +
> > + return m88e_config_init(phydev);
> > +}
>
> Hi Robert
On Mon, 2020-10-19 at 22:08 +0100, Russell King - ARM Linux admin
wrote:
> On Mon, Oct 19, 2020 at 02:49:13PM -0600, Robert Hancock wrote:
> > The Finisar FCLF8520P2BTL 1000BaseT SFP module uses a Marvel
> > 81E PHY
>
> You mean 88E here.
>
Whoops, will f
some special handling to ensure that 1000BaseT auto-
negotiation is enabled properly when desired.
Based on existing handling in the AMD xgbe driver and the information in
the Finisar FAQ:
https://www.finisar.com/sites/default/files/resources/an-2036_1000base-t_sfp_faqreve1.pdf
Signed-off-by: Robert
Update the axienet driver to properly support the Xilinx PCS/PMA PHY
component which is used for 1000BaseX and SGMII modes, including
properly configuring the auto-negotiation mode of the PHY and reading
the negotiated state from the PHY.
Signed-off-by: Robert Hancock
---
drivers/net/ethernet
Thanks.
/Robert
On Tue, 29 Sep 2020 at 19:25, Priyaranjan Jha wrote:
>
> The BBR ACK aggregation patches have been packported to 4.19 kernel,
> and are part of v4.19.148 stable release:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/log/?h=v4.19
While up-streaming the IPQ4019 driver it was thought that the controller had no
Clause 45 support,
but it actually does and its activated by writing a bit to the mode register.
So lets add it as newer SoC-s use the same controller and Clause 45 compliant
PHY-s.
Signed-off-by: Robert Marko
Cc
On Mon, Sep 21, 2020 at 11:48 PM David Miller wrote:
>
> From: Robert Marko
> Date: Sun, 20 Sep 2020 16:16:51 +0200
>
> > This patch series adds support for Clause 45 to the driver.
> >
> > While at it also change some defines to upper case to match rest of the
>
configuration has been found
Robert Marko (2):
net: mdio-ipq4019: change defines to upper case
net: mdio-ipq4019: add Clause 45 support
drivers/net/mdio/mdio-ipq4019.c | 109 +++-
1 file changed, 92 insertions(+), 17 deletions(-)
--
2.26.2
In the commit adding the IPQ4019 MDIO driver, defines for timeout and sleep
partially used lower case.
Lets change it to upper case in line with the rest of driver defines.
Signed-off-by: Robert Marko
Cc: Luka Perkov
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
---
Changes since v4
Good Day, I am glad to contact you through this medium I’m Sgt Vivian Robert am
from united state, 28 years old single I am the only surviving child of my late
parents, I am America female soldier presently in Afghanistan for the training,
advising the Afghan forces and also helping in
; Otherwise this looks O.K.
>
> Andrew
v4 has been pushed to address your comment
Regards,
Robert
This patch series adds support for Clause 45 to the driver.
While at it also change some defines to upper case to match rest of the driver.
Changes since v1:
* Drop clock patches, these need further investigation and
no user for non default configuration has been found
Robert Marko (2):
net
While up-streaming the IPQ4019 driver it was thought that the controller had no
Clause 45 support,
but it actually does and its activated by writing a bit to the mode register.
So lets add it as newer SoC-s use the same controller and Clause 45 compliant
PHY-s.
Signed-off-by: Robert Marko
Cc
In the commit adding the IPQ4019 MDIO driver, defines for timeout and sleep
partially used lower case.
Lets change it to upper case in line with the rest of driver defines.
Signed-off-by: Robert Marko
Cc: Luka Perkov
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
---
drivers/net/phy
In the commit adding the IPQ4019 MDIO driver, defines for timeout and sleep
partially used lower case.
Lets change it to upper case in line with the rest of driver defines.
Signed-off-by: Robert Marko
Cc: Luka Perkov
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
---
drivers/net/phy
While up-streaming the IPQ4019 driver it was thought that the controller had no
Clause 45 support,
but it actually does and its activated by writing a bit to the mode register.
So lets add it as newer SoC-s use the same controller and Clause 45 compliant
PHY-s.
Signed-off-by: Robert Marko
Cc
This patch series adds support for Clause 45 to the driver.
While at it also change some defines to upper case to match rest of the driver.
Changes since v1:
* Drop clock patches, these need further investigation and
no user for non default configuration has been found
Robert Marko (2):
net
While up-streaming the IPQ4019 driver it was thought that the controller had no
Clause 45 support,
but it actually does and its activated by writing a bit to the mode register.
So lets add it as newer SoC-s use the same controller and Clause 45 compliant
PHY-s.
Signed-off-by: Robert Marko
Cc
This patch series adds support for Clause 45 to the driver.
While at it also change some defines to upper case to match rest of the driver.
Changes since v1:
* Drop clock patches, these need further investigation and
no user for non default configuration has been found
Robert Marko (2):
net
In the commit adding the IPQ4019 MDIO driver, defines for timeout and sleep
partially used lower case.
Lets change it to upper case in line with the rest of driver defines.
Signed-off-by: Robert Marko
Cc: Luka Perkov
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
---
drivers/net/phy
Much appreciated.
Thank you everyone.
/Robert
On Mon, 24 Aug 2020 at 20:39, Priyaranjan Jha wrote:
>
> Thank you, Eric, Robert.
> We will try to provide the backport for the patch soon.
>
> Thanks,
> Priyaranjan
>
> (resending since previous reply bounced back)
> O
feed through ffmpeg to MistServer.
Best regards
/Robert
--
Robert Bengtsson-Ölund, System Developer
Software Development
+46(0)90-349 39 00
www.intinor.com
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On Thu, Jul 2, 2020 at 9:59 PM Florian Fainelli wrote:
>
>
>
> On 7/2/2020 3:29 AM, Robert Marko wrote:
> > Some newer SoC-s have a separate MDIO clock that needs to be enabled.
> > So lets add support for handling the clocks to the driver.
> >
&
On Thu, Jul 2, 2020 at 10:04 PM Florian Fainelli wrote:
>
>
>
> On 7/2/2020 12:18 PM, Robert Marko wrote:
> > On Thu, Jul 2, 2020 at 3:38 PM Andrew Lunn wrote:
> >>
> >>> + clock-frequency:
> >>> +default: 1
> >>
> >
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