Hi Bjorn
On Mon, Jun 29, 2020 at 02:33:16PM -0500, Bjorn Helgaas wrote:
> [+cc Ashok, Ding, Casey]
>
> On Mon, Jun 29, 2020 at 12:32:44PM +0300, Aya Levin wrote:
> > I wanted to turn on RO on the ETH driver based on
> > pcie_relaxed_ordering_enabled().
> > From my experiments I see that pcie_rel
On Mon, Aug 14, 2017 at 11:44:57PM +0800, Ding Tianhong wrote:
> Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe
> Root Port where Upstream Transaction Layer Packets with the Relaxed
> Ordering Attribute clear are allowed to bypass earlier TLPs with
> Relaxed Ordering set, it would
On Wed, Aug 09, 2017 at 04:46:07PM +, Casey Leedom wrote:
> | From: Raj, Ashok
> | Sent: Wednesday, August 9, 2017 8:58 AM
> | ...
> | As Casey pointed out in an earlier thread, we choose the heavy hammer
> | approach because there are some that can lead to data-corruption as
Hi Bjorn
On Tue, Aug 08, 2017 at 06:22:00PM -0500, Bjorn Helgaas wrote:
> On Sat, Aug 05, 2017 at 03:15:10PM +0800, Ding Tianhong wrote:
> > From: Casey Leedom
> >
> > Root complexes don't obey PCIe 3.0 ordering rules, hence could lead to
> > data-corruption.
>
> This needs to include a link to
On Fri, Aug 04, 2017 at 08:20:37PM +, Casey Leedom wrote:
> | From: Raj, Ashok
> | Sent: Thursday, August 3, 2017 1:31 AM
> |
> | I don't understand this completely.. So your driver would know not to send
> | RO TLP's to root complex. But you want to send RO to the
Hi Ding
patch looks good, except would reword the patch description for clarity
here is my crack at it, feel free to use.
On Thu, Jul 13, 2017 at 10:21:31PM +0800, Ding Tianhong wrote:
> The PCIe Device Control Register use the bit 4 to indicate that
> whether the device is permitted to enable r
Hi Ding
Not sure if V7 is the last version.
can you consider rewording this just to make it a little bit more
readable? My suggestion below, feel free to use/modify
Otherwise its all good and you can add my Ack.
Acked-by: Ashok Raj
On Thu, Jul 13, 2017 at 10:21:30PM +0800, Ding Tianhong wrote
Hi Casey
On Wed, Aug 02, 2017 at 05:53:52PM +, Casey Leedom wrote:
> Okay, here you go. As you can tell, it's almost a trivial copy of the
> cxgb4 patch.
>
> By the way, I realized that we have yet another hole which is likely not
> to be fixable. If we're dealing with a problematic Ro
Hi Casey
> | Still no Intel and AMD guys has ack this, this is what I am worried about,
> | should I ping some man again ?
I can ack the patch set for Intel specific changes. Now that the doc is made
public :-).
Can you/Ding resend the patch series, i do have the most recent v7, some
of the com
On Tue, May 02, 2017 at 11:10:22AM -0700, Alexander Duyck wrote:
> On Tue, May 2, 2017 at 9:53 AM, Raj, Ashok wrote:
> > On Tue, May 02, 2017 at 09:39:34AM -0700, Alexander Duyck wrote:
> >> On Mon, May 1, 2017 at 4:13 PM, Casey Leedom wrote:
> >> > The new flag PCI
On Tue, May 02, 2017 at 09:39:34AM -0700, Alexander Duyck wrote:
> On Mon, May 1, 2017 at 4:13 PM, Casey Leedom wrote:
> > The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
> > Ordering Attribute should not be used on Transaction Layer Packets destined
> > for the PCIe End
Hi Casey
On Mon, May 01, 2017 at 04:13:50PM -0700, Casey Leedom wrote:
> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
> Ordering Attribute should not be used on Transaction Layer Packets destined
> for the PCIe End Node so flagged. Initially flagged this way are Inte
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