On Tue, 20 Apr 2021 14:24:19 +0100, Jon Hunter wrote:
> Commit 300bb1fe7671 ("ptp: arm/arm64: Enable ptp_kvm for arm/arm64")
> enable ptp_kvm support for ARM platforms and for any ARM platform that
> does not support this, the following error message is displayed ...
>
> ERR KERN fail to initiali
On Sat, 17 Apr 2021 09:59:39 +0100,
Zenghui Yu wrote:
>
> On 2021/3/30 22:54, Marc Zyngier wrote:
> > +PTP_KVM support for arm/arm64
> > +=
> > +
> > +PTP_KVM is used for high precision time sync between host and guests.
> > +It r
On Sat, 17 Apr 2021 09:42:37 +0100,
Zenghui Yu wrote:
>
> On 2021/3/30 22:54, Marc Zyngier wrote:
> > +int kvm_arch_ptp_init(void)
> > +{
> > + int ret;
> > +
> > + ret = kvm_arm_hyp_service_available(ARM_SMCCC_KVM_FUNC_PTP);
> > + if (ret <= 0)
On Tue, 13 Apr 2021 01:07:23 +0100,
Andrew Lunn wrote:
>
> > > > +static void
> > > > +mt7530_setup_mdio_irq(struct mt7530_priv *priv)
> > > > +{
> > > > + struct dsa_switch *ds = priv->ds;
> > > > + int p;
> > > > +
> > > > + for (p = 0; p < MT7530_NUM_PHYS; p++) {
> > > > +
On Mon, 12 Apr 2021 04:42:35 +0100,
DENG Qingfang wrote:
>
> Add support for MT7530 interrupt controller to handle internal PHYs.
> In order to assign an IRQ number to each PHY, the registration of MDIO bus
> is also done in this driver.
>
> Signed-off-by: DENG Qingfang
> ---
> RFC v3 -> RFC v4
On Wed, 07 Apr 2021 16:13:34 +0100,
Richard Cochran wrote:
>
> On Wed, Apr 07, 2021 at 10:28:44AM +0100, Marc Zyngier wrote:
> > On Tue, 30 Mar 2021 15:54:26 +0100,
> > Marc Zyngier wrote:
> > >
> > > From: Jianyong Wu
> > >
> > > Curren
On Tue, 30 Mar 2021 15:54:26 +0100,
Marc Zyngier wrote:
>
> From: Jianyong Wu
>
> Currently, the ptp_kvm module contains a lot of x86-specific code.
> Let's move this code into a new arch-specific file in the same directory,
> and rename the arch-independent f
From: Jianyong Wu
Add clocksource id to the ARM generic counter so that it can be easily
identified from callers such as ptp_kvm.
Cc: Mark Rutland
Reviewed-by: Andre Przywara
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-6
From: Jianyong Wu
Currently, the ptp_kvm module contains a lot of x86-specific code.
Let's move this code into a new arch-specific file in the same directory,
and rename the arch-independent file to ptp_kvm_common.c.
Reviewed-by: Andre Przywara
Signed-off-by: Jianyong Wu
Signed-off-by:
From: Jianyong Wu
Implement the hypervisor side of the KVM PTP interface.
The service offers wall time and cycle count from host to guest.
The caller must specify whether they want the host's view of
either the virtual or physical counter.
Signed-off-by: Jianyong Wu
Signed-off-by:
take the snapshot and act accordingly.
Signed-off-by: Thomas Gleixner
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-5-jianyong...@arm.com
---
include/linux/clocksource.h | 6 ++
include/linux/clocksource_ids.h | 11
yong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-8-jianyong...@arm.com
---
drivers/clocksource/arm_arch_timer.c | 34
drivers/ptp/Kconfig | 2 +-
drivers/ptp/Makefile | 1 +
drivers/pt
From: Will Deacon
We can advertise ourselves to guests as KVM and provide a basic features
bitmap for discoverability of future hypervisor services.
Cc: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r
tible with KVM. Once this has been established,
additional services can be discovered via a feature bitmap.
Reviewed-by: Steven Price
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
[maz: move code to its own file, plug it into PSCI]
Signed-off-by: Marc Zyngier
Link: https://lore.ke
Given that this series[0] has languished in my Inbox for the best of the
past two years, and in an effort to eventually get it merged, I've
taken the liberty to pick it up and do the changes I wanted to see
instead of waiting to go through yet another round.
All the patches have a link to their or
From: Jianyong Wu
Implement the hypervisor side of the KVM PTP interface.
The service offers wall time and cycle count from host to guest.
The caller must specify whether they want the host's view of
either the virtual or physical counter.
Signed-off-by: Jianyong Wu
Signed-off-by:
yong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-8-jianyong...@arm.com
---
drivers/clocksource/arm_arch_timer.c | 34
drivers/ptp/Kconfig | 2 +-
drivers/ptp/Makefile | 1 +
drivers/pt
From: Jianyong Wu
Add clocksource id to the ARM generic counter so that it can be easily
identified from callers such as ptp_kvm.
Cc: Mark Rutland
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-6-jianyong...@arm.com
---
drivers
From: Jianyong Wu
Currently, the ptp_kvm module contains a lot of x86-specific code.
Let's move this code into a new arch-specific file in the same directory,
and rename the arch-independent file to ptp_kvm_common.c.
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link:
take the snapshot and act accordingly.
Signed-off-by: Thomas Gleixner
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-5-jianyong...@arm.com
---
include/linux/clocksource.h | 6 ++
include/linux/clocksource_ids.h | 11
tible with KVM. Once this has been established,
additional services can be discovered via a feature bitmap.
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
[maz: move code to its own file, plug it into PSCI]
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-
From: Will Deacon
We can advertise ourselves to guests as KVM and provide a basic features
bitmap for discoverability of future hypervisor services.
Cc: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r
Given that this series[0] has languished in my Inbox for the best of the
past two years, and in an effort to eventually get it merged, I've
taken the liberty to pick it up and do the changes I wanted to see
instead of waiting to go through yet another round.
All the patches have a link to their or
On 2021-02-05 11:19, Will Deacon wrote:
On Fri, Feb 05, 2021 at 09:11:00AM +, Steven Price wrote:
On 02/02/2021 14:11, Marc Zyngier wrote:
> diff --git a/drivers/firmware/smccc/kvm_guest.c
b/drivers/firmware/smccc/kvm_guest.c
> new file mode 100644
> index ..23c
On 2021-02-05 11:19, Will Deacon wrote:
On Fri, Feb 05, 2021 at 09:11:00AM +, Steven Price wrote:
On 02/02/2021 14:11, Marc Zyngier wrote:
> diff --git a/drivers/firmware/smccc/kvm_guest.c
b/drivers/firmware/smccc/kvm_guest.c
> new file mode 100644
> index ..23c
On 2020-12-09 06:09, Jianyong Wu wrote:
Let userspace check if there is kvm ptp service in host.
Before VMs migrate to another host, VMM may check if this
cap is available to determine the next behavior.
Signed-off-by: Jianyong Wu
Suggested-by: Marc Zyngier
---
arch/arm64/kvm/arm.c | 1
Given that this series[0] has languished in my Inbox for the best of the
past two years, and in an effort to eventually get it merged, I've
taken the liberty to pick it up and do the changes I wanted to see
instead of waiting to go through yet another round.
All the patches have a link to their or
tible with KVM. Once this has been established,
additional services can be discovered via a feature bitmap.
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
[maz: move code to its own file, plug it into PSCI]
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-
From: Jianyong Wu
Add clocksource id to the ARM generic counter so that it can be easily
identified from callers such as ptp_kvm.
Cc: Mark Rutland
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-6-jianyong...@arm.com
---
drivers
From: Jianyong Wu
Currently, the ptp_kvm module contains a lot of x86-specific code.
Let's move this code into a new arch-specific file in the same directory,
and rename the arch-independent file to ptp_kvm_common.c.
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link:
take the snapshot and act accordingly.
Signed-off-by: Thomas Gleixner
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-5-jianyong...@arm.com
---
include/linux/clocksource.h | 6 ++
include/linux/clocksource_ids.h | 11
From: Will Deacon
We can advertise ourselves to guests as KVM and provide a basic features
bitmap for discoverability of future hypervisor services.
Cc: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r
On 2020-12-09 06:09, Jianyong Wu wrote:
Currently, we offen use ntp (sync time with remote network clock)
to sync time in VM. But the precision of ntp is subject to network
delay
so it's difficult to sync time in a high precision.
kvm virtual ptp clock (ptp_kvm) offers another way to sync time
yong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-8-jianyong...@arm.com
---
drivers/clocksource/arm_arch_timer.c | 31
drivers/ptp/Kconfig | 2 +-
drivers/ptp/Makefile | 1 +
drivers/pt
From: Jianyong Wu
Implement the hypervisor side of the KVM PTP interface.
The service offers wall time and cycle count from host to guest.
The caller must specify whether they want the host's view of
either the virtual or physical counter.
Signed-off-by: Jianyong Wu
Signed-off-by:
On 2020-12-09 06:09, Jianyong Wu wrote:
PTP_KVM implementation depends on hypercall using SMCCC. So we
introduce a new SMCCC service ID. This doc explains how does the
ID define and how does PTP_KVM works on arm/arm64.
Signed-off-by: Jianyong Wu
---
Documentation/virt/kvm/api.rst | 9
On 2020-12-09 06:09, Jianyong Wu wrote:
Currently, there is no mechanism to keep time sync between guest and
host
in arm/arm64 virtualization environment. Time in guest will drift
compared
with host after boot up as they may both use third party time sources
to correct their time respectively.
On 2020-12-09 06:09, Jianyong Wu wrote:
ptp_kvm will get this service through SMCC call.
The service offers wall time and cycle count of host to guest.
The caller must specify whether they want the host cycle count
or the difference between host cycle count and cntvoff.
Signed-off-by: Jianyong W
On 2020-12-09 06:09, Jianyong Wu wrote:
Currently, ptp_kvm modules implementation is only for x86 which
includes
large part of arch-specific code. This patch moves all of this code
into a new arch related file in the same directory.
Signed-off-by: Jianyong Wu
---
drivers/ptp/Makefile
rm arch to let arm kvm guest use
this service.
Cc: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
---
arch/arm/kernel/setup.c| 5
arch/arm64/kernel/setup.c | 1 +
drivers/firmware/smccc/smccc.c | 37 +
include/linux/arm-smccc.h
Hi Qingfang,
On 2020-12-30 04:22, DENG Qingfang wrote:
Hi,
I added MT7530 IRQ support and registered its internal PHYs to IRQ.
It works but my patch used two hacks.
1. Removed phy_drv_supports_irq check, because config_intr and
handle_interrupt are not set for Generic PHY.
2. Allocated ds->sl
On Thu, 10 Dec 2020 19:25:46 +,
Thomas Gleixner wrote:
>
> The irq descriptor is already there, no need to look it up again.
>
> Signed-off-by: Thomas Gleixner
> Cc: Mark Rutland
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Marc Zyngier
> Cc: linux-arm
On Thu, 10 Dec 2020 19:25:45 +,
Thomas Gleixner wrote:
>
> The irq descriptor is already there, no need to look it up again.
>
> Signed-off-by: Thomas Gleixner
> Cc: Marc Zyngier
> Cc: Russell King
> Cc: linux-arm-ker...@lists.infradead.org
> ---
> arch/arm/
On 2020-11-24 05:20, Jianyong Wu wrote:
Hi Marc,
[...]
> +/* ptp_kvm counter type ID */
> +#define ARM_PTP_VIRT_COUNTER 0
> +#define ARM_PTP_PHY_COUNTER 1
> +#define ARM_PTP_NONE_COUNTER 2
The architecture definitely doesn't hav
Jianyong,
On 2020-11-24 05:37, Jianyong Wu wrote:
Hi Marc,
[...]
> +
arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FU
NC_ID,
> + ARM_PTP_NONE_COUNTER, &hvc_res);
I really don't see the need to use a non-architectural counter ID.
Using the virtual counter ID
On 2020-11-23 10:44, Marc Zyngier wrote:
On 2020-11-11 06:22, Jianyong Wu wrote:
ptp_kvm will get this service through SMCC call.
The service offers wall time and cycle count of host to guest.
The caller must specify whether they want the host cycle count
or the difference between host cycle
On 2020-11-11 06:22, Jianyong Wu wrote:
PTP_KVM implementation depends on hypercall using SMCCC. So we
introduce a new SMCCC service ID. This doc explains how does the
ID define and how does PTP_KVM works on arm/arm64.
Signed-off-by: Jianyong Wu
---
Documentation/virt/kvm/api.rst | 9
On 2020-11-11 06:22, Jianyong Wu wrote:
Currently, there is no mechanism to keep time sync between guest and
host
in arm/arm64 virtualization environment. Time in guest will drift
compared
with host after boot up as they may both use third party time sources
to correct their time respectively.
On 2020-11-11 06:22, Jianyong Wu wrote:
ptp_kvm will get this service through SMCC call.
The service offers wall time and cycle count of host to guest.
The caller must specify whether they want the host cycle count
or the difference between host cycle count and cntvoff.
Signed-off-by: Jianyong W
On Fri, 2 Oct 2020 07:49:44 +0200, Mauro Carvalho Chehab wrote:
> There are some new warnings when building the documentation from
> yesterday's linux next. This small series fix them.
>
> - patch 1 documents two new kernel-doc parameters on a net core file.
> I used the commit log in order to h
On 2020-09-07 10:28, Jianyong Wu wrote:
-Original Message-
From: Marc Zyngier
Sent: Monday, September 7, 2020 4:55 PM
To: Jianyong Wu
[...]
>>arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_FEATUR
>> ES_FUNC_ID,
>> > + &hvc_res)
On 2020-09-07 09:40, Jianyong Wu wrote:
Hi Marc,
-Original Message-
From: Marc Zyngier
Sent: Saturday, September 5, 2020 7:02 PM
To: Jianyong Wu
Cc: netdev@vger.kernel.org; yangbo...@nxp.com; john.stu...@linaro.org;
t...@linutronix.de; pbonz...@redhat.com;
sean.j.christopher
On Sat, 05 Sep 2020 12:01:42 +0100,
Marc Zyngier wrote:
>
> On Fri, 04 Sep 2020 10:27:42 +0100,
> Jianyong Wu wrote:
[...]
> > +{
> > + ktime_t ktime;
> > +
> > + arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
> > +
On Fri, 04 Sep 2020 10:27:42 +0100,
Jianyong Wu wrote:
>
> Currently, there is no mechanism to keep time sync between guest and host
> in arm64 virtualization environment. Time in guest will drift compared
> with host after boot up as they may both use third party time sources
> to correct their
On Fri, 04 Sep 2020 10:27:41 +0100,
Jianyong Wu wrote:
>
> ptp_kvm will get this service through smccc call.
> The service offers wall time and counter cycle of host for guest.
> caller must explicitly determines which cycle of virtual counter or
> physical counter to return if it needs counter c
On Fri, 04 Sep 2020 10:27:42 +0100,
Jianyong Wu wrote:
>
> Currently, there is no mechanism to keep time sync between guest and host
> in arm64 virtualization environment. Time in guest will drift compared
> with host after boot up as they may both use third party time sources
> to correct their
On Fri, 04 Sep 2020 10:27:43 +0100,
Jianyong Wu wrote:
>
> ptp_kvm implementation depends on hypercall using SMCCC. So we
> introduce a new SMCCC service ID. This doc explain how we define
> and use this new ID.
>
> Signed-off-by: Jianyong Wu
> ---
> Documentation/virt/kvm/arm/ptp_kvm.rst | 72
On Fri, 04 Sep 2020 10:27:41 +0100,
Jianyong Wu wrote:
>
> ptp_kvm will get this service through smccc call.
> The service offers wall time and counter cycle of host for guest.
> caller must explicitly determines which cycle of virtual counter or
> physical counter to return if it needs counter c
86e81)
syz repro:
https://syzkaller.appspot.com/x/repro.syz?x=127d3c9990
The issue was bisected to:
commit a9ed4a6560b8562b7e2e2bed9527e88001f7b682
Author: Marc Zyngier
Date: Wed Aug 19 16:12:17 2020 +
epoll: Keep a reference on files added to the check list
All of
On 2020-05-25 15:18, Jianyong Wu wrote:
Hi Marc,
-Original Message-
From: Marc Zyngier
Sent: Monday, May 25, 2020 5:17 PM
To: Richard Cochran ; Jianyong Wu
Cc: netdev@vger.kernel.org; yangbo...@nxp.com; john.stu...@linaro.org;
t...@linutronix.de; pbonz...@redhat.com
On 2020-05-24 03:11, Richard Cochran wrote:
On Fri, May 22, 2020 at 04:37:23PM +0800, Jianyong Wu wrote:
In general, vm inside will use virtual counter compered with host use
phyical counter. But in some special scenarios, like nested
virtualization, phyical counter maybe used by vm. A interface
BREAK_FAULT;
> esz = 32;
> break;
> case AARCH64_INSN_VARIANT_64BIT:
> @@ -1556,6 +1550,12 @@ static u32 aarch64_encode_immediate(u64 imm,
> return AARCH64_BREAK_FAULT;
> }
>
> + mask = GENMASK(esz - 1, 0);
> +
> + /* Can't encode full zeroes or full ones */
... nor a value wider than the mask.
> + if (imm & ~mask || !imm || imm == mask)
> + return AARCH64_BREAK_FAULT;
> +
> /*
>* Inverse of Replicate(). Try to spot a repeating pattern
>* with a pow2 stride.
>
>
> What do you think?
I'd be pretty happy with that.
Reviewed-by: Marc Zyngier
Thanks,
M.
--
Jazz is not dead. It just smells funny...
Hi Luke,
Thanks a lot for nailing these bugs.
On Wed, 6 May 2020 18:05:01 -0700
Luke Nelson wrote:
> This patch fixes two issues present in the current function for encoding
> arm64 logical immediates when using the 32-bit variants of instructions.
>
> First, the code does not correctly rejec
On 11/04/2019 09:18, Guillaume Gardet wrote:
> Hi,
>
> With kernel 5.0 and 5.1-rc4, we encounter OOPS in nf_getsockopt on aarch64
> (on Raspberry Pi3 and qemu).
> This can be triggered with podman or iptables/ip6tables.
> The easiest way to reproduce is with 'iptables -F output' and it will trigg
On 08/03/2019 08:26, Kalle Valo wrote:
> Marc Zyngier writes:
>
>> For quite some time, I wondered why the PCI mwifiex device built in my
>> Chromebook was unable to use the good old legacy interrupts. But as MSIs
>> were working fine, I never really bothered invest
+ Lorenzo
Hi Brian,
On 26/02/2019 23:28, Brian Norris wrote:
> + others
>
> Hi Marc,
>
> Thanks for the series. I have a few bits of history to add to this, and
> some comments.
>
> On Sun, Feb 24, 2019 at 02:04:22PM +, Marc Zyngier wrote:
>> For quite som
On 26/02/2019 23:44, Brian Norris wrote:
> Hi,
>
> On Tue, Feb 26, 2019 at 05:14:00PM +0000, Marc Zyngier wrote:
>> On 26/02/2019 16:21, Ard Biesheuvel wrote:
>>> On Mon, 25 Feb 2019 at 15:53, Marc Zyngier wrote:
>>>> It outlines one thing: If you have to inte
On 26/02/2019 16:21, Ard Biesheuvel wrote:
> On Mon, 25 Feb 2019 at 15:53, Marc Zyngier wrote:
>>
>> Hi Ard,
>>
>> On 25/02/2019 12:45, Ard Biesheuvel wrote:
>>> On Sun, 24 Feb 2019 at 15:08, Marc Zyngier wrote:
>>>>
>>>> For quite
Hi Ard,
On 25/02/2019 12:45, Ard Biesheuvel wrote:
> On Sun, 24 Feb 2019 at 15:08, Marc Zyngier wrote:
>>
>> For quite some time, I wondered why the PCI mwifiex device built in my
>> Chromebook was unable to use the good old legacy interrupts. But as MSIs
>> were w
thus change the binding to be somewhat compatible with the spec,
by placing the wake-up interrupt in a subnode called "wake-up". This
still is an optional property, but a recommended one for PCI devices.
Signed-off-by: Marc Zyngier
---
.../bindings/net/wireless/marvell-8
/wakeup subsystem. Oops.
The right way to handle this kind of situation is to flag the
interrupt with IRQ_NOAUTOEN before requesting it. It will then
stay disabled until someone (the wake-up subsystem) enables it.
Signed-off-by: Marc Zyngier
---
drivers/net/wireless/marvell/mwifiex/main.c | 2 +-
1
ebook range, which all use the same broken
configuration.
With all that, I finally have PCI legacy interrupts working with the mwifiex
driver on my Chromebook.
[1] http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
Marc Zyngier (4):
dt-bindings/marvell-8xxx: Allow wake-up inter
In order to get PCIe legacy interrupts working on gru-based Chromebooks,
let's move the wake-up interrupt out of the way and into its own
subnode. This ensures that this interrupt specifier will not be
mistaken as a PCI interrupt.
Signed-off-by: Marc Zyngier
---
arch/arm64/boot/dts/roc
pts in case MSIs are unavailable.
Signed-off-by: Marc Zyngier
---
drivers/net/wireless/marvell/mwifiex/main.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/marvell/mwifiex/main.c
b/drivers/net/wireless/marvell/mwifiex/main.c
index 20cee5c397fb..2105c
(no actual deadlock occurs), and is
fixed in a similar way to c6894dec8ea9 ("bridge: fix lockdep
addr_list_lock false positive splat") by putting the addr_list_lock
in its own lockdep class.
Signed-off-by: Marc Zyngier
---
net/dsa/master.c | 4
1 file changed, 4 insertions(+)
di
On Sat, 29 Dec 2018 00:02:57 +,
Stefan Wahren wrote:
Hi Stephan,
>
> Hi,
> while booting my Raspberry Pi 3 B+ with Linux 4.20 (arm64/defconfig)
> i'm getting the following warning:
>
> [ 11.005738] irq 79 handler irq_default_primary_handler+0x0/0x8 enabled
> interrupts
[...]
> This se
On 30/10/18 15:10, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 Oct 2018 14:55:01 +0000, Marc Zyngier wrote:
>
>>> I.e, isn't the firmware fix papering over a bug that should be fixed in
>>> Linux mvpp2 driver anyway ?
>>
>> Absolutely. L
On 30/10/18 13:00, Thomas Petazzoni wrote:
> Hello Marcin,
>
> Thanks for the feedback.
>
> On Tue, 30 Oct 2018 13:37:37 +0100, Marcin Wojtas wrote:
>
>> You use _really_ archaic firmware, the bug you see is 99% caused by a
>> bug already fixed long time ago (cleanup all PP2 BM pools correctly
>
Marcin,
On 30/10/18 12:37, Marcin Wojtas wrote:
> [Resend in UTF-8]
>
> Hi Marc,
>
> You use _really_ archaic firmware, the bug you see is 99% caused by a
Please let me fix this for you:
s/_really_ archaic/released/
> bug already fixed long time ago (cleanup all PP2 BM pools correctly
> durin
Antoine,
On 30/10/18 10:50, Antoine Tenart wrote:
> Marc,
>
> On Mon, Oct 29, 2018 at 03:05:53PM +0000, Marc Zyngier wrote:
>>
>> This is a follow-up on the conversation Thomas and I had last week at
>> ELC, with me ranting at the sorry state of the MVPP2 driver.
&g
On Mon, 2 Apr 2018 07:43:49 +
Alexander Kurz wrote:
> Remove the duplicated code for asix88179_178a bind and reset methods.
>
> Signed-off-by: Alexander Kurz
> ---
> drivers/net/usb/ax88179_178a.c | 137
> ++---
> 1 file changed, 31 insertions(+), 106 d
[dropping Freddy as I'm getting bounces from asix.com.tw]
On Mon, 2 Apr 2018 15:21:08 + Alexander Kurz wrote:
Alexander,
> Hi Marc, David,
> with the v2 patch ("net: usb: asix88179_178a: de-duplicate code")
> I made an embarrasly stupid mistake of removing the wrong function.
> The v2 patch
On Mon, 02 Apr 2018 08:43:49 +0100,
Alexander Kurz wrote:
Alexander,
>
> Remove the duplicated code for asix88179_178a bind and reset methods.
>
> Signed-off-by: Alexander Kurz
> ---
> drivers/net/usb/ax88179_178a.c | 137
> ++---
> 1 file changed, 31 inse
Alexander, David,
On 2018-03-08 11:19, Alexander Kurz wrote:
Remove the duplicated code for asix88179_178a bind and reset methods.
Signed-off-by: Alexander Kurz
---
drivers/net/usb/ax88179_178a.c | 117
+++--
1 file changed, 31 insertions(+), 86 deletions(-
Chen
> Signed-off-by: Greentime Hu
Reviewed-by: Marc Zyngier
Once there is an agreement on this series being fit for mainline, let me
know how you want to get this merged (either as a whole series, or with
this driver going through the irq tree).
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On 08/12/17 11:54, Greentime Hu wrote:
> Hi, Mark:
>
> 2017-12-08 18:21 GMT+08:00 Mark Rutland :
>> On Fri, Dec 08, 2017 at 05:12:00PM +0800, Greentime Hu wrote:
>>> From: Greentime Hu
>>>
>>> This patch adds VDSO support. The VDSO code is currently used for
>>> sys_rt_sigreturn() and optimised g
On Wed, Nov 29 2017 at 11:23:34 pm GMT, Greentime Hu wrote:
Hi Greentime,
>>> +}
>>> +
>>> +static void ativic32_mask_ack_irq(struct irq_data *data)
>>> +{
>>> + unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
>>> + __nds32__mtsr_dsb(int_mask2 & (~(1 << data->hwirq)),
>>> NDS32_
On 27/11/17 12:28, Greentime Hu wrote:
> From: Greentime Hu
>
> This patch adds the Andestech Internal Vector Interrupt Controller
> driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual.
> http://www.andestech.com/product.php?cls=9
>
> Signed-off-by: Rick Chen
> Signed-off-by: Gr
On 08/11/17 05:55, Greentime Hu wrote:
> From: Greentime Hu
>
Please add a commit message, indicating what this does, and potentially
a pointer to some documentation (if publicly available).
> Signed-off-by: Rick Chen
> Signed-off-by: Greentime Hu
> ---
> drivers/irqchip/Makefile |
userspace from interacting
with these interrupts altogether.
Cc: sta...@vger.kernel.org
Signed-off-by: Marc Zyngier
---
drivers/net/ethernet/marvell/mvpp2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c
b/drivers/net/ethernet/marvell/mvpp2.c
ind
fat warning when CONFIG_DEBUG_PREEMPT=y.
>
> Therefore, this commit replaces the smp_processor_id() in
> migration-enabled contexts by the appropriate get_cpu/put_cpu sections.
>
> Reported-by: Marc Zyngier
> Fixes: a786841df72e ("net: mvpp2: handle register mapping and
Hi Geert,
On 08/11/16 19:35, Geert Uytterhoeven wrote:
> Currently the renesas-irqc driver uses postcore_initcall().
>
> However, the new CPG/MSSR driver uses subsys_initcall(). Hence the
> IRQC's probe will be deferred, which causes the Micrel Ethernet PHY to
> not find its interrupt on R-Car Ge
On 02/09/16 11:06, Zubair Lutfullah Kakakhel wrote:
> Hi,
>
> On 09/02/2016 07:25 AM, Michal Simek wrote:
>> On 1.9.2016 18:50, Zubair Lutfullah Kakakhel wrote:
>>> The Xilinx AXI Interrupt Controller IP block is used by the MIPS
>>> based xilfpga platform.
>>>
>>> Move the interrupt controller co
On 01/09/16 17:50, Zubair Lutfullah Kakakhel wrote:
> The drivers read/write function handling is a bit quirky.
> And the irqmask is passed directly to the handler.
>
> Add a new irqchip struct to pass to the handler and
> cleanup read/write handling.
>
> Signed-off-by: Zubair Lutfullah Kakakhel
On 01/09/16 17:50, Zubair Lutfullah Kakakhel wrote:
> The MIPS based xilfpga platform has the following IRQ structure
>
> Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
>
> Add support for the driver to chain the irq handler
>
> Signed-off-by: Zubair Lutfullah Kakakhel
>
> ---
On 01/09/16 14:52, Zubair Lutfullah Kakakhel wrote:
> Hi,
[...]
>> But that still doesn't address the case I had in mind, which is when you
>> have *two* AXI-intc, one cascaded into the other. Is that something that
>> could be built? You should at least make sure that there is a big fat
>> warni
On 01/09/16 12:01, Zubair Lutfullah Kakakhel wrote:
> Hi,
>
> Thanks for the review
> Comments inline.
>
> On 08/31/2016 05:57 PM, Marc Zyngier wrote:
>> On 31/08/16 17:35, Zubair Lutfullah Kakakhel wrote:
>>> The MIPS based xilfpga platform has the following
On 31/08/16 17:35, Zubair Lutfullah Kakakhel wrote:
> The MIPS based xilfpga platform has the following IRQ structure
>
> Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
>
> Add support for the driver to chain the irq handler
>
> Signed-off-by: Zubair Lutfullah Kakakhel
>
> ---
On 31/08/16 17:35, Zubair Lutfullah Kakakhel wrote:
> The drivers read/write function handling is a bit quirky.
> And the irqmask is passed directly to the handler.
>
> Add a new irqchip struct to pass to the handler and
> cleanup read/write handling.
>
> Signed-off-by: Zubair Lutfullah Kakakhel
On Thu, 18 Aug 2016 14:43:16 +0100
Zubair Lutfullah Kakakhel wrote:
> The MIPS based xilfpga platform has the following IRQ structure
>
> Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
>
> Add support for the driver to chain the irq handler
>
> Signed-off-by: Zubair Lutfullah
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