On 2019-09-17 5:36 p.m., Arlie Davis wrote:
> Likewise, I'm at a loss for testing with real hardware. It's hard to
> find such things, now.
How does de2104x compare to ds2142/43? I have a c3750 with ds2142/43 tulip.
Helge
or some others might have a machine with a de2104x.
Dave
8] ---[ end Kernel panic - not syncing: Attempted to kill init!
exitcode=0x000b ]---
Dave
--
John David Anglin dave.ang...@bell.net
On 2019-02-11 6:33 p.m., Andrew Lunn wrote:
>> Signed-off-by: John David Anglin
>> ---
>> drivers/net/dsa/mv88e6xxx/chip.c | 28 ++--
>> 1 file changed, 22 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/net/dsa/mv88e6xxx/ch
edge when a new event occurs.
Tested on espressobin board.
Signed-off-by: John David Anglin
---
drivers/net/dsa/mv88e6xxx/chip.c | 28 ++--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
inate it, at some point it is going to hit you.
You could be right but I don't want to give up just yet. I need to go
back and rebuild v4.20.4 and retest.
My hunch is the second hunk of the original patch will fix this.
Dave
--
John David Anglin dave.ang...@bell.net
On 2019-02-04 6:14 p.m., Andrew Lunn wrote:
> On Mon, Feb 04, 2019 at 04:59:13PM -0500, John David Anglin wrote:
>> This change fixes a race condition in the setup of hardware irqs and the
>> code enabling PHY link detection in the mv88e6xxx driver.
>>
>> This race was
_setup_masks(chip);
+ if (err)
+ return err;
+
err = mv88e6xxx_g1_irq_setup_common(chip);
if (err)
return err;
Signed-off-by: John David Anglin
--
John David Anglin dave.ang...@bell.net
interrupts in the global control register does
not affect their status.
Thus, at worst, the hunk adds a bit of unnecessary code. It could be
skipped if we knew we
were using level interrupts.
Dave
--
John David Anglin dave.ang...@bell.net
see that an interrupt might be handled twice if the source wasn't
cleared before interrupts
are re-enabled but I think that would also occur with level interrupts.
Dave
--
John David Anglin dave.ang...@bell.net
;
+ err = mv88e6xxx_g1_irq_setup_masks(chip);
+ if (err)
+ return err;
+
err = mv88e6xxx_g1_irq_setup_common(chip);
if (err)
return err;
Signed-off-by: John David Anglin
--
John David Anglin dave.ang...@bell.net
On 2019-01-30 8:27 p.m., John David Anglin wrote:
> On 2019-01-30 5:38 p.m., Andrew Lunn wrote:
>> I'd suggest you take a look at the datasheet for the 37xx and check
>> what the hardware actually supports. You might need to extend the
>> driver.
> I did look a
in
generic ARM documents that I don't currently have. I'll see if I can
find them tomorrow.
Dave
--
John David Anglin dave.ang...@bell.net
side, DTC no longer objects to level interrupts on southbridge.
Dave
--
John David Anglin dave.ang...@bell.net
On 2019-01-30 12:28 p.m., Andrew Lunn wrote:
> On Wed, Jan 30, 2019 at 12:08:39PM -0500, John David Anglin wrote:
>> On 2019-01-22 7:22 p.m., Andrew Lunn wrote:
>>> >From my Espressobin
>>>
>>> cat /proc/interrupts
>>> ...
>>> 44:
M
loading is done. Another possibility might be race conditions
in processing interrupts.
Thoughts?
Dave
--
John David Anglin dave.ang...@bell.net
regulator only
switches the I/O voltage.
The attached change fixed reboot on espressobin with problematic SD card.
Thanks,
Dave
--
John David Anglin dave.ang...@bell.net
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
inde
#x27;t handle AVB interrupts, I started down this
path to try get ptp4l working better. I
have tweaked the polling but there are still circumstances where
timestamps are overwritten (or not written).
Dave
--
John David Anglin dave.ang...@bell.net
diff --git a/arch/arm64/boot/dts/marvell/arma
esses to get at
the PHY registers in the 88E6341.
Can you point me to the phylib code that does the polling?
Thanks,
Dave
--
John David Anglin dave.ang...@bell.net
t its IP address from DHCP.
Your configuration is different. I have the wan, lan0 and lan1 ports
configured as a bridge and they
don't get IP addresses. The only port that gets an IP is br0.
Dave
--
John David Anglin dave.ang...@bell.net
faces are coming up in reverse
order: lan1->lan0->wan.
Need to check eth0 relative to the others.
Dave
--
John David Anglin dave.ang...@bell.net
ed. I disabled the networkmanager service.
However, DHCP
on br0 didn't always get an IP. It was after disabling networkmanager
that the ports didn't
come up on boot.
Dave
--
John David Anglin dave.ang...@bell.net
stemd-networkd[358]: lan0: Configured
--
John David Anglindave.ang...@bell.net
tate still doesn't update if a cable
is disconnected or moved.
I'm puzzled as to how this is supposed to work. Thoughts?
Regards,
Dave Anglin
--
John David Anglin dave.ang...@bell.net
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 9b8dd0d0ee42..c1ec13b320ee 1006
location of
the file is "/usr/include/hppa-linux-gnu/sys/uio.h".
Dave
--
John David Anglin dave.ang...@bell.net
t; but if it is actually real...
See page 10 in this document:
https://parisc.wiki.kernel.org/images-parisc/e/e9/PA-8700wp.pdf
It shows the PA-8700 L1 design. James' comments and this paper are the
basis for this change.
Dave
--
John David Anglin dave.ang...@bell.net
--
To
calls. This
whole discussion started when I
suggested that we needed to bump L1_CACHE_BYTES to 128 bytes on PA8800 and
PA8900 processors.
--
John David Anglin dave.ang...@bell.net
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