On Thu, Apr 15, 2021 at 12:14 AM Ezequiel Garcia wrote:
>
> Hi Peter, Heiko,
>
> On Wed, 2021-04-14 at 13:15 +0200, Heiko Stübner wrote:
> > Am Mittwoch, 14. April 2021, 13:03:25 CEST schrieb Peter Geis:
> > > On Tue, Apr 13, 2021 at 7:37 PM Ezequiel Garcia
> > > wrote:
> > > > > > +static void
Hi Stephen,
On Wed, Mar 17, 2021 at 06:56:05PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the net-next tree, today's linux-next build (sparc64
> defconfig) produced this warning:
>
> drivers/net/ethernet/intel/e1000e/netdev.c:6926:12: warning:
> 'e1000e_pm_prepare' defined but no
Hi Jakub,
thanks for taking a look!
On Mon, Mar 15, 2021 at 02:04:22PM -0700, Jakub Kicinski wrote:
> On Mon, 15 Mar 2021 12:02:30 -0700 Tony Nguyen wrote:
> > +static __maybe_unused int e1000e_pm_prepare(struct device *dev)
> > +{
> > + return pm_runtime_suspended(dev) &&
> > + pm_susp
ot;.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> Adjust the spacing and use an explicit "return 0" in the success path
> to make the function easier to parse.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> Use the appropriate function instead of reimplementing it,
> and update the error message to match the code.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> sun8i_dwmac_unpower_internal_phy already checks if the PHY is powered,
> so there is no need to do it again here.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> This is a deinitialization function that always returned zero, and that
> return value was always ignored. Have it return void instead.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
ver
> removal callback. Also ensure the EPHY is powered down before removal.
>
> Fixes: 634db83b8265 ("net: stmmac: dwmac-sun8i: Handle integrated/external
> MDIOs")
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
: stmmac: Add dwmac-sun8i")
> Fixes: 40a1dcee2d18 ("net: ethernet: dwmac-sun8i: Use the correct function in
> exit path")
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Wed, Dec 16, 2020 at 4:16 AM Christophe JAILLET
wrote:
>
> Le 15/12/2020 à 20:35, Dan Carpenter a écrit :
> > On Tue, Dec 15, 2020 at 08:08:15PM +0100, Maxime Ripard wrote:
> >> On Tue, Dec 15, 2020 at 07:18:48PM +0100, Christophe JAILLET wrote:
> >>> Le 15/12/2020 à 12:37, Maxime Ripard a écri
Hi Kai-Heng,
On Wed, Dec 02, 2020 at 09:06:19PM +0800, Kai-Heng Feng wrote:
> > ---
> > v2: Added test data and some commit log revise(Paul Menzel)
> >Only skip the suspend/resume if the NIC is not a wake up device specified
> >by the user(Kai-Heng Feng)
> > v3: Leverage direct complete mec
uld support runtime suspend, disabling the
runtime suspend on them by default would impact the validation.
Only disable runtime suspend on CNP in case of any user space regression.
Signed-off-by: Chen Yu
---
drivers/net/ethernet/intel/e1000e/netdev.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
Suggested-by: Kai-Heng Feng
Signed-off-by: Chen Yu
---
v2: Added test data and some commit log revise(Paul Menzel)
Only skip the suspend/resume if the NIC is not a wake up device specified
by the user(Kai-Heng Feng)
v3: Leverage direct complete mechanism to skip all hooks(Kai-Heng Feng)
manipulate S0ix settings during suspend.
Chen Yu (2):
e1000e: Leverage direct_complete to speed up s2ram
e1000e: Remove the runtime suspend restriction on CNP+
drivers/net/ethernet/intel/e1000e/netdev.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
--
2.17.1
[ 494.957615] e1000e :00:19.0: pci_pm_resume+0x0/0x90 returned 0 after 177
usecs
Signed-off-by: Chen Yu
---
v2: Added test data and some commit log revise(Paul Menzel)
Only skip the suspend/resume if the NIC is not a wake up device specified
by the user(Kai-Heng Feng)
--
drivers/base/power
uld support runtime suspend, disabling the
runtime suspend on them by default would impact the validation.
Signed-off-by: Chen Yu
---
drivers/net/ethernet/intel/e1000e/netdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c
b/drivers/
/resume
process a lot.
Chen Yu (2):
e1000e: Assign DPM_FLAG_SMART_SUSPEND and DPM_FLAG_MAY_SKIP_RESUME to
speed up s2ram
e1000e: Remove the runtime suspend restriction on CNP+
drivers/base/power/main.c | 2 ++
drivers/net/ethernet/intel/e1000e/netdev.c | 21
On Tue, Jun 16, 2020 at 02:51:27AM +0800, Brown, Aaron F wrote:
> > From: Chen Yu
> > Sent: Thursday, May 21, 2020 10:59 AM
> > To: Kirsher, Jeffrey T ; David S. Miller
> > ; Jakub Kicinski ; Kok, Auke-jan H
> > ; Jeff Garzik
> > Cc: intel-wired-...@list
Hi Sasha,
On Tue, May 26, 2020 at 12:23:55AM +, Sasha Levin wrote:
> Hi
>
> [This is an automated email]
>
> This commit has been processed because it contains a "Fixes:" tag
> fixing commit: bc7f75fa9788 ("[E1000E]: New pci-express e1000 driver
> (currently for ICH9 devices only)").
>
> Th
On Sun, May 24, 2020 at 11:06:53PM +0200, Michal Kubecek wrote:
> On Sat, May 23, 2020 at 05:09:50PM +0800, Chen Yu wrote:
> > Hi Michal,
> > Thanks for reviewing,
> > and sorry for late reply.
> > On Thu, May 21, 2020 at 09:23:42PM +0200, Michal Kubecek wrote:
> >
Hi Michal,
Thanks for reviewing,
and sorry for late reply.
On Thu, May 21, 2020 at 09:23:42PM +0200, Michal Kubecek wrote:
> On Fri, May 22, 2020 at 01:59:13AM +0800, Chen Yu wrote:
> > Currently the ethtool shows that WOL(Wake On Lan) is enabled
> > even if the device wakeup a
wake up ability for this device.
Fixes: 6ff68026f475 ("e1000e: Use device_set_wakeup_enable")
Reported-by: Len Brown
Reviewed-by: Andy Shevchenko
Cc:
Signed-off-by: Chen Yu
---
drivers/net/ethernet/intel/e1000e/ethtool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
.
This patch clears the WOL ability of this network device if the
user has disabled the wake up ability in sysfs.
Fixes: bc7f75fa9788 ("[E1000E]: New pci-express e1000 driver")
Reported-by: Rafael J. Wysocki
Reviewed-by: Andy Shevchenko
Cc:
Signed-off-by: Chen Yu
---
drivers/net/ethe
Currently the WOL(Wake On Lan) bahavior of e1000e is not consistent with its
corresponding
device wake up ability.
Fix this by:
1. Do not wake up the system via WOL if device wakeup is disabled
2. Make WOL display info from ethtool consistent with device wake up
settings in sysfs
Chen Yu (2
On Thu, Jun 27, 2019 at 11:32 PM Maxime Ripard
wrote:
>
> The phy device tree property has been deprecated in favor of phy-handle,
> let's replace it.
>
> Signed-off-by: Maxime Ripard
This patch breaks Ethernet on all my dwmac-sunxi, i.e. old GMAC, boards, with
the following error messages:
.
>
> Changes from v1:
> - New patch
> ---
> arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 6 +++---
Tested-by: Chen-Yu Tsai
On Wed, Feb 20, 2019 at 5:09 AM David Summers
wrote:
>
> On 19/02/2019 14:17, Rob Herring wrote:
> > On Mon, Feb 18, 2019 at 4:28 PM Vasily Khoruzhick
> > wrote:
> >> On Mon, Feb 18, 2019 at 2:08 PM Stefan Wahren
> >> wrote:
> >>> Hi Vasily,
> >> Hi Stefan,
> >>
> Vasily Khoruzhick hat a
On Sat, Jan 19, 2019 at 1:02 AM Vasily Khoruzhick wrote:
>
> Some boards (e.g. Pine64 and Pinebook) wire a GPIO to reset pin of
> RTL8723BS
Pine64 / Pinebook don't have the enable pin. One could say that the
enable pin and the reset pin you add here are actually the same thing.
ChenYu
> Signed-
On Mon, May 14, 2018 at 1:03 AM, Maxime Ripard
wrote:
> 1;5201;0c
> On Sun, May 13, 2018 at 12:37:49PM -0700, Chen-Yu Tsai wrote:
>> On Wed, May 2, 2018 at 4:54 AM, Maxime Ripard
>> wrote:
>> > On Wed, May 02, 2018 at 06:19:51PM +0800, Icenowy Zheng wrote:
>>
On Sun, May 13, 2018 at 1:29 PM, Andrew Lunn wrote:
> On Sun, May 13, 2018 at 01:11:08PM -0700, Chen-Yu Tsai wrote:
>> On Sun, May 13, 2018 at 1:05 PM, Andrew Lunn wrote:
>> >> > Hi Chen-Yu
>> >> >
>> >> > Are these delays the MAC applies?
On Sun, May 13, 2018 at 1:05 PM, Andrew Lunn wrote:
>> > Hi Chen-Yu
>> >
>> > Are these delays the MAC applies? Not the PHY. It would be good to
>> > make it clear here these are MAC imposed delays.
>>
>> Yes these are applied on the MAC side. Be
On Sun, May 13, 2018 at 12:49 PM, Andrew Lunn wrote:
> On Mon, May 14, 2018 at 03:14:18AM +0800, Chen-Yu Tsai wrote:
>> The clock delay chains found in the glue layer for dwmac-sun8i are only
>> used with RGMII PHYs. They are not intended for non-RGMII PHYs, such as
>> MII
On Wed, May 2, 2018 at 4:54 AM, Maxime Ripard wrote:
> On Wed, May 02, 2018 at 06:19:51PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年5月2日 GMT+08:00 下午5:53:21, Chen-Yu Tsai 写到:
>> >On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard
>> > wrote:
>> >>
chain section of the device tree binding
to make it clear that the delay chains only apply to RGMII PHYs, and
make it easier to add the R40-specific bits later.
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Rob Herring
Acked-by: Maxime Ripard
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt
The A83T syscon compatible was appended to the syscon compatibles list,
instead of inserted in to preserve the ordering.
Move it to the proper place to keep the list sorted.
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Rob Herring
Acked-by: Maxime Ripard
---
Documentation/devicetree/bindings/net
d_update_bits(),
but this is not done here to keep the patch simple.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 42 ++-
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stm
drivers to register custom
syscon devices with their own regmap and locking.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (8):
dt-bindings: net: dwmac-sun8i: Clean up clock delay chain descriptions
dt-bindings: net: dwmac-sun8i: Sort syscon compatibles by alphabetical
order
dt-bindings:
p tied to it. We can then get the device
from the existing syscon phandle, and retrieve the regmap with
dev_get_regmap().
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 50 ++-
1 file changed, 49 insertions(+), 1 deletion(-)
d RX delay chain, and no TX delay chain.
This patch adds support for it using the framework laid out by previous
patches to map the differences.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 17 +
1 file changed, 17
d RX delay chain, and no TX delay chain.
This patch adds the R40 specific bits to the dwmac-sun8i binding.
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Rob Herring
Acked-by: Maxime Ripard
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 3 +++
1 file changed, 3 insertions(+)
di
;syscon" device type is more of an implementation detail. There are many
ways to access a register not in a device's address range, the syscon
interface being the most generic and unrestricted one.
Simplify the description so that it says what it is supposed to
describe.
Signed-off-by:
is not supported or absent.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 32 +--
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet
On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard wrote:
> Hi,
>
> On Wed, May 02, 2018 at 12:12:27AM +0800, Chen-Yu Tsai wrote:
>> From: Icenowy Zheng
>>
>> Allwinner A64 has a SRAM controller, and in the device tree currently
>> we have a syscon node to enable EMA
On Wed, May 2, 2018 at 12:12 AM, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This is v2 of my R40 Ethernet support series.
>
> Changes since v1:
>
> - Default to fetching regmap from device pointed to by syscon phandle,
> and falling back to syscon API if tha
The device nodes dereference (&foo) usages should be sorted by the label
names, barring any parsing order issues such as the #include statement
for the PMIC's .dtsi file that must come after the PMIC.
Move the mmc and ohci blocks in front of the PMIC's regulator blocks.
Signed-o
GMAC is labeled "gmac_mdio".
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 173dcc1652d2..bd97ca3dc2fa 10
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 39
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c3aa839a453d 100644
--- a/drivers
The A83T syscon compatible was appended to the syscon compatibles list,
instead of inserted in to preserve the ordering.
Move it to the proper place to keep the list sorted.
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 2
d RX delay chain, and no TX delay chain.
This patch adds support for it using the framework laid out by previous
patches to map the differences.
Signed-off-by: Chen-Yu Tsai
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 17 +
1 file changed, 17 insertions(+)
diff --git
is not supported or absent.
Signed-off-by: Chen-Yu Tsai
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 32 +--
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
d RX delay chain, and no TX delay chain.
This patch adds the R40 specific bits to the dwmac-sun8i binding.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dwmac-su
i M2 Ultra.
Patches 14 and 15 are for the A64. They convert the existing syscon
device to an SRAM controller device that exports a regmap. The needed
driver changes are in patch 14, and the device tree changes are in
patch 15.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (11):
dt-bindings:
,
and let EMAC driver to acquire its EMAC clock regmap.
Signed-off-by: Icenowy Zheng
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
Zheng
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 33
1 file changed, 33 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index c3aa839a453d..65ba6455feb7 100644
--- a/drivers/clk/sunxi-n
chain section of the device tree binding
to make it clear that the delay chains only apply to RGMII PHYs, and
make it easier to add the R40-specific bits later.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 11 +++
1 file changed, 7 insertions(+), 4
p tied to it. We can then get the device
from the existing syscon phandle, and retrieve the regmap with
dev_get_regmap().
Signed-off-by: Chen-Yu Tsai
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 50 ++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/
;syscon" device type is more of an implementation detail. There are many
ways to access a register not in a device's address range, the syscon
interface being the most generic and unrestricted one.
Simplify the description so that it says what it is supposed to
describe.
Si
The Bananapi M2 Ultra has a Realtek RTL8211E RGMII PHY tied to the GMAC.
The PMIC's DC1SW output provides power for the PHY, while the ALDO2
output provides I/O voltages on both sides.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 30 +++
1
d_update_bits(),
but this is not done here to keep the patch simple.
Signed-off-by: Chen-Yu Tsai
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 42 ++-
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/
accessible and drop regmap name]
Signed-off-by: Chen-Yu Tsai
---
drivers/soc/sunxi/sunxi_sram.c | 57 --
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index 882be5ed7e84..eec7fc6e9f66
Hi Rob,
On Tue, Apr 17, 2018 at 7:17 AM, Icenowy Zheng wrote:
>
>
> 于 2018年4月17日 GMT+08:00 上午2:47:45, Rob Herring 写到:
>>On Wed, Apr 11, 2018 at 10:16:37PM +0800, Icenowy Zheng wrote:
>>> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i
>>is
>>> in another device's memory spac
On Tue, Apr 17, 2018 at 7:52 PM, Maxime Ripard
wrote:
> On Mon, Apr 16, 2018 at 10:51:55PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
>> wrote:
>> > On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>> >> On Th
On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
wrote:
> On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng wrote:
>> > 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
>> > 写到:
>> >>On Wed, Ap
On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng wrote:
>
>
> 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
> 写到:
>>On Wed, Apr 11, 2018 at 10:16:39PM +0800, Icenowy Zheng wrote:
>>> From: Chen-Yu Tsai
>>>
>>> On the Allwinner R40 SoC, the &q
On Wed, Apr 4, 2018 at 2:45 PM, Icenowy Zheng wrote:
> 在 2018-04-03二的 11:50 +0200，Maxime Ripard写道：
>> On Tue, Apr 03, 2018 at 11:48:45AM +0200, Maxime Ripard wrote:
>> > On Tue, Mar 20, 2018 at 03:15:02PM +0800, Chen-Yu Tsai wrote:
>> > > On Mon, Mar 19,
On Tue, Apr 3, 2018 at 5:54 PM, Icenowy Zheng wrote:
>
>
> 于 2018年4月3日 GMT+08:00 下午5:53:08, Chen-Yu Tsai 写到:
>>On Tue, Apr 3, 2018 at 5:50 PM, Maxime Ripard
>> wrote:
>>> On Tue, Apr 03, 2018 at 11:48:45AM +0200, Maxime Ripard wrote:
>>>> On Tue, Mar
On Tue, Apr 3, 2018 at 5:50 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 11:48:45AM +0200, Maxime Ripard wrote:
>> On Tue, Mar 20, 2018 at 03:15:02PM +0800, Chen-Yu Tsai wrote:
>> > On Mon, Mar 19, 2018 at 5:31 AM, Maxime Ripard
>> > wrote:
>> > > O
On Sun, Mar 18, 2018 at 5:21 PM, Sergei Shtylyov
wrote:
> Hello!
>
>
> On 3/17/2018 12:28 PM, Chen-Yu Tsai wrote:
>
>> The clock delay chains found in the glue layer for dwmac-sun8i are only
>> used with RGMII PHYs. They are not intended for non-RGMII PHYs, such as
On Mon, Mar 19, 2018 at 5:31 AM, Maxime Ripard
wrote:
> On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote:
>> From: Icenowy Zheng
>>
>> There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in
>> the syscon part, in the CCU of R40 SoC.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 39 ++--
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c3aa839a453d 100644
--- a
The device nodes dereference (&foo) usages should be sorted by the label
names, barring any parsing order issues such as the #include statement
for the PMIC's .dtsi file that must come after the PMIC.
Move the mmc and ohci blocks in front of the PMIC's regulator blocks.
Signed-o
d RX delay chain, and no TX delay chain.
This patch adds support for it using the framework laid out by previous
patches to map the differences.
Signed-off-by: Chen-Yu Tsai
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 18 ++
1 file changed, 18 insertions(+)
diff --git
Zheng
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index c3aa839a453d..54c7a6106206 100644
--- a/drivers/clk/sun
The A83T syscon compatible was appended to the syscon compatibles list,
instead of inserted in to preserve the ordering.
Move it to the proper place to keep the list sorted.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 2 +-
1 file changed, 1
is not supported or absent.
Signed-off-by: Chen-Yu Tsai
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 32 ---
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac
d_update_bits(),
but this is not done here to keep the patch simple.
Signed-off-by: Chen-Yu Tsai
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 42 +--
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/
d RX delay chain, and no TX delay chain.
This patch adds the R40 specific bits to the dwmac-sun8i binding.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dwmac-su
registers.
Instead, for these types of setups, we let the CCU register a proper
device and a regmap tied to it. We can then get the device from the
phandle, and retrieve the regmap with dev_get_regmap().
Signed-off-by: Chen-Yu Tsai
---
drivers/net/ethernet/stmicro/stmmac/dwmac-su
GMAC is labeled "gmac_mdio".
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 173dcc1652d2..bd97ca3dc2fa 10
The Bananapi M2 Ultra has a Realtek RTL8211E RGMII PHY tied to the GMAC.
The PMIC's DC1SW output provides power for the PHY, while the ALDO2
output provides I/O voltages on both sides.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
ode pinmux setting for the
R40.
Patch 12 enables Ethernet on the Bananapi M2 Ultra.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (10):
dt-bindings: net: dwmac-sun8i: Clean up clock delay chain descriptions
dt-bindings: net: dwmac-sun8i: Sort syscon compatibles by alphabetical
chain section of the device tree binding
to make it clear that the delay chains only apply to RGMII PHYs, and
make it easier to add the R40-specific bits later.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 11 +++
1 file changed, 7 insertions(+), 4
On Wed, Nov 29, 2017 at 11:46 PM, Andrew Lunn wrote:
> Hi ChenYu
>
>> It worked at one point. During some previous iteration, they lit up as
>> they were supposed to.
>
> For a released version of the kernel? Or during development work? If
> they did work, but broken, it would be good to know whi
On Wed, Nov 29, 2017 at 11:37 PM, Andrew Lunn wrote:
> On Wed, Nov 29, 2017 at 10:02:40AM +0100, Corentin Labbe wrote:
>> On Tue, Nov 28, 2017 at 06:38:26PM +0100, Andrew Lunn wrote:
>> > On Tue, Nov 28, 2017 at 05:48:22PM +0100, Corentin Labbe wrote:
>> > > The driver expect "allwinner,leds-activ
On Fri, Sep 8, 2017 at 3:36 PM, Corentin Labbe
wrote:
> On Fri, Sep 08, 2017 at 09:19:54AM +0200, Maxime Ripard wrote:
>> On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:
>> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
>> > b/arch/arm64/boot/dts/allwinner/
> arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 8 ---
I think this particular change is in -next, not v4.13-rc.
Otherwise, whole series is
Acked-by: Chen-Yu Tsai
> arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 --
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
On Fri, Aug 25, 2017 at 11:05 AM, Florian Fainelli wrote:
>
>
> On 08/24/2017 07:54 PM, Chen-Yu Tsai wrote:
>> On Fri, Aug 25, 2017 at 3:59 AM, Florian Fainelli
>> wrote:
>>> On 08/24/2017 01:21 AM, Corentin Labbe wrote:
>>>> On Wed, Aug 23, 2017 a
On Fri, Aug 25, 2017 at 3:59 AM, Florian Fainelli wrote:
> On 08/24/2017 01:21 AM, Corentin Labbe wrote:
>> On Wed, Aug 23, 2017 at 09:31:53AM -0700, Florian Fainelli wrote:
>>> On 08/23/2017 12:49 AM, Maxime Ripard wrote:
Hi Florian,
On Tue, Aug 22, 2017 at 11:35:01AM -0700, Floria
On Mon, Aug 21, 2017 at 10:23 PM, Andrew Lunn wrote:
>> All muxes are mostly always represented the same way afaik, or do you
>> want to simply introduce a new compatible / property?
>
> + mdio-mux {
> + compatible = "allwinner,sun8i-h3-mdio-switch";
> + mdio-pa
On Sun, Aug 20, 2017 at 10:25 PM, Andrew Lunn wrote:
>> I think we cannot use mdio-mux-mmioreg since the register for doing
>> the switch is in middle of the "System Control" and shared with
>> other functions. This is why we use a sycon/regmap for selecting
>> the MDIO.
>
> You could add a mdio-
On Fri, Aug 18, 2017 at 8:21 PM, Corentin Labbe
wrote:
> In case of a MDIO switch, the registered MDIO node should be
> the parent of the PHY. Otherwise of_phy_connect will fail.
>
> Signed-off-by: Corentin Labbe
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 ++--
>
Y, so it is modified to a boolean soc_has_internal_phy.
>
> Signed-off-by: Corentin Labbe
Acked-by: Chen-Yu Tsai
On Fri, Aug 18, 2017 at 8:21 PM, Corentin Labbe
wrote:
> This patch add documentation about the MDIO switch used on sun8i-h3-emac
> for integrated PHY.
>
> Signed-off-by: Corentin Labbe
> ---
> .../devicetree/bindings/net/dwmac-sun8i.txt| 112
> +++--
> 1 file changed, 1
On Fri, Aug 11, 2017 at 4:19 PM, Corentin Labbe
wrote:
> On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe
>> wrote:
>> > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote:
>> >> Hi,
&
On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe
wrote:
> On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe
>> wrote:
>> > This patch add the new phy-is-integrated property to the internal
Hi,
On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe
wrote:
> This patch add the new phy-is-integrated property to the internal PHY
> node.
>
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/sunx
On Thu, Aug 10, 2017 at 8:20 AM, Andrew Lunn wrote:
> On Wed, Aug 09, 2017 at 03:47:34PM -0700, Florian Fainelli wrote:
>> On August 9, 2017 5:10:30 AM PDT, David Wu wrote:
>> >Add the documentation for internal phy. A boolean property
>> >indicates that a internal phy will be used.
>> >
>> >Sign
Hi David,
On Wed, Aug 9, 2017 at 5:38 PM, David.Wu wrote:
> Hello Corentin, Chen-Yu
>
>
> 在 2017/8/9 16:45, Corentin Labbe 写道:
>>
>> On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
>>>
>>> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli
&
On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli wrote:
> On 08/01/2017 11:21 PM, David Wu wrote:
>> To make internal phy work, need to configure the phy_clock,
>> phy cru_reset and related registers.
>>
>> Signed-off-by: David Wu
>> ---
>> .../devicetree/bindings/net/rockchip-dwmac.txt | 6
1 - 100 of 131 matches
Mail list logo
