on the
pushbuf, which is easiest to verify when it's in non-symbolic form.
With these two minor items corrected, this series is
Reviewed-by: Ilia Mirkin
Same suggestion as Ilia.
This series is:
Reviewed-by: Samuel Pitoiset
PUSH_DATA (push, 0x1);
if (unlikely(info->indirect
On 06/29/2016 03:55 PM, Hans de Goede wrote:
Hi,
On 29-06-16 15:27, Ilia Mirkin wrote:
For those of us who are lazy and forgetful (i.e. me), can you remind
the difference between auto_ptr and unique_ptr? IIRC unique_ptr is
more like scoped_ptr, while auto_ptr has transfer semantics?
Actuall
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 122245c..7d8549a 100644
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 3580b33..276e8d3 100644
--- a
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 276e8d3..122245c 100644
--- a
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 7d8549a..d88bdce 100644
--- a
ll up.
Signed-off-by: Ilia Mirkin
Reviewed-by: Samuel Pitoiset
---
Only tested on GK208... probably would be good for someone on GF1xx to give it
a shot.
Tested on GF119 (ie. piglit-run -t arb_shader_image_load_store ...),
works fine.
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 55 ++
1 file changed, 55 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 3213188
This instruction is new since SM50 (Maxwell) and allows to perform
an add with three sources. Unfortunately, it only supports integers.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h| 1 +
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 928923c..f136c58
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 34 ++
1 file changed, 34 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 2c5e8f6
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index f136c58..1cf1fa3
d in shared programs :22128 -> 22128 (0.00%)
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 62 ++
1 file changed, 62 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/n
And ADD3(d, a, 0x0, c) to ADD(d, a, c) as well.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium
This is similar to what we already do for MAD/FMA.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium
On 07/01/2016 12:40 AM, Ilia Mirkin wrote:
Doesn't ADD3 only work for integers? I don't see anything here
preventing float adds from being merged here...
isOpSupported() should do the job because I check if dtype is float.
On Thu, Jun 30, 2016 at 6:26 PM, Samuel Pitoiset
wrot
I was not sure about moveSources() because we have two variants and the
other one doesn't move the modifiers.
On Thu, Jun 30, 2016 at 6:26 PM, Samuel Pitoiset
wrote:
And ADD3(d, a, 0x0, c) to ADD(d, a, c) as well.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/n
On 07/01/2016 06:19 AM, Ilia Mirkin wrote:
On Thu, Jun 30, 2016 at 6:54 PM, Samuel Pitoiset
wrote:
On 07/01/2016 12:44 AM, Ilia Mirkin wrote:
If moveSources doesn't move modifiers, we have a serious problem.
However it looks like it does:
void
Instruction::setSrc(int s, const Val
On 07/02/2016 12:23 PM, Hans de Goede wrote:
Hi,
On 29-06-16 15:41, Ilia Mirkin wrote:
On Wed, Jun 29, 2016 at 8:37 AM, Hans de Goede
wrote:
Add support for SV_WORK_DIM for nvc0 and nve4.
Signed-off-by: Hans de Goede
---
Changes in v2
-Use new NVC0_CB_AUX_GRID_INFO(i) version
Changes in v
When emitting OP_SUB, the sign bit for FADD and FADD32I is not
at the same position. It's at position 45 for FADD but 51 for FADD32I.
This fixes the following piglit test:
tests/spec/arb_fragment_program/fdo30337b.shader_test
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/no
actually because it is not set
for that source. I didn't check the other emitters but that test passes
on GK107 (and probably on GF100/GK110 as well).
As an aside, how did you hit this? Should have gotten folded in...
With piglit. :)
On Jul 4, 2016 7:12 AM, "Samue
In presence of an indirect image access, the base offset should be
zeroed because the stride will be computed twice. This is a pretty
rare situation but it can happen when tex.r > 0.
Signed-off-by: Samuel Pitoiset
Cc: "11.2 12.0"
---
src/gallium/drivers/nouveau/codegen/nv50_ir_
While we are at it, fix a typo inside the comment which describes
what those constants are for.
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 98 +++---
1 file changed, 49 insertions(+), 49 deletions(-)
diff --git a/src/gallium/drivers
On 07/05/2016 12:57 AM, Ilia Mirkin wrote:
This makes the code identical to the new code I added in suq handling?
If so, r-b. As a separate patch, I'd encourage a refactor of the logic.
Sure, this was my plan too.
On Jul 4, 2016 6:08 PM, "Samuel Pitoiset" mailto:samuel.pit
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 124 +++--
.../nouveau/codegen/nv50_ir_lowering_nvc0.h| 2 +-
2 files changed, 44 insertions(+), 82 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 24 --
.../nouveau/codegen/nv50_ir_lowering_nvc0.h| 4
2 files changed, 28 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src
This fixes the following piglits:
arb_arrays_of_arrays-basic-imagestore-mixed-const-non-const-uniform-index
arb_arrays_of_arrays-basic-imagestore-mixed-const-non-const-uniform-index2
Signed-off-by: Samuel Pitoiset
Cc: 12.0
---
Expect minor conflicts because I did refactor that logic but the
On 07/10/2016 04:23 PM, Ilia Mirkin wrote:
Do you also need to zero out su->tex.r ?
Nope, because it's only used when rIndirectSrc < 0 (ie. no indirection).
On Jul 10, 2016 10:19 AM, "Samuel Pitoiset" mailto:samuel.pitoi...@gmail.com>> wrote:
This
The size of the driver constant buffer for each stage should be 2048
and not 512 because it has been increased recently for buffers/images.
While we are at it, do the same change for indirect draws.
This fixes all ARB_shader_draw_parameters tests on GM107.
Signed-off-by: Samuel Pitoiset
Cc
This might avoid mistakes if the size is bumped in the future.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 8
src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 4 ++--
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 2
Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM")
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouve
Reviewed-by: Samuel Pitoiset
On 07/17/2016 11:18 PM, Ilia Mirkin wrote:
Mark both L8_SRGB and L8A8_SRGB as non-renderable (the latter already
didn't have the bind flags). This makes the state tracker pick a
different format when rendering is required, or mark the fb as
incomplete. This
because we expose 8 images.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
b/src/gallium/drivers/nouveau/nvc0
ic" support for images but it should work
in most cases.
Please review,
Thanks!
Samuel Pitoiset (8):
nvc0: increase the tex handles area size in the driver cb
nvc0: bind images for 3d/cp shaders on GM107+
gm107/ir: lower surface operations
gm107/ra: fix constraints for surface operat
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 76 +-
.../nouveau/codegen/nv50_ir_lowering_nvc0.h| 2 +
2 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0
On Maxwell, images binding is slightly different (and much better)
regarding Fermi and Kepler because a texture view needs to be uploaded
for each image and this is going to simplify the thing a lot.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 5
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 25 --
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 63fe9c0
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 105 +
1 file changed, 105 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index
MS images have to be handled explicitly and I don't plan to implement
them for now.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/dr
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index ae0dd78..22f2f5d 100644
--- a/src
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 50 ++
1 file changed, 50 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 871ffd2
Works fine on Fermi, but still need to test on Kepler1.
On 07/16/2016 09:09 PM, Ilia Mirkin wrote:
This is useful for pbo downloads, which are now accelerated with images.
BGRA8 is a moderately common format to do that in.
Signed-off-by: Ilia Mirkin
---
This needs testing on SM20 and SM30. I'
On 07/18/2016 11:16 PM, Ilia Mirkin wrote:
Karol tested it on Kepler1, so we should be good.
Reviewed-by: Samuel Pitoiset
On Mon, Jul 18, 2016 at 5:15 PM, Samuel Pitoiset
wrote:
Works fine on Fermi, but still need to test on Kepler1.
On 07/16/2016 09:09 PM, Ilia Mirkin wrote:
This
On 07/18/2016 11:13 PM, Ilia Mirkin wrote:
On Mon, Jul 18, 2016 at 4:55 PM, Samuel Pitoiset
wrote:
On Maxwell, images binding is slightly different (and much better)
regarding Fermi and Kepler because a texture view needs to be uploaded
for each image and this is going to simplify the thing
And ADD3(d, a, 0x0, c) to ADD(d, a, c) as well.
v2: - use moveSources()
- allow ADD3 -> ADD when srcFlags is set
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gall
And ADD3(d, a, b, c) to ADD(d, b, a + c) as well.
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 62 ++
1 file changed, 62 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers
This instruction is new since SM50 (Maxwell) and allows to perform
an add with three sources. Unfortunately, it only supports integers.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h| 1 +
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
This is similar to what we already do for MAD/FMA.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index ceb9718..77bac82
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 77bac82..ec6418b
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 34 ++
1 file changed, 34 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index f1ba27a
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 55 ++
1 file changed, 55 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 3fc1abf
Like FADD32I, the NEG modifier of src0 is at position 56.
Signed-off-by: Samuel Pitoiset
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/codegen
ADD only allows to emit 19-bits immediates.
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers
On 07/19/2016 05:56 PM, Ilia Mirkin wrote:
Reviewed-by: Ilia Mirkin
Please put together some shader tests for this, and verify that this
fix is not necessary on earlier SM versions.
Okay, will do.
On Tue, Jul 19, 2016 at 8:47 AM, Samuel Pitoiset
wrote:
ADD only allows to emit 19-bits
On 07/19/2016 06:11 PM, Ilia Mirkin wrote:
On Mon, Jul 18, 2016 at 4:56 PM, Samuel Pitoiset
wrote:
MS images have to be handled explicitly and I don't plan to implement
them for now.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 7 +++
1
On 07/19/2016 07:14 PM, Józef Kucia wrote:
On Mon, Jul 18, 2016 at 10:55 PM, Samuel Pitoiset
wrote:
+ } else if (insn->tex.target == TEX_TARGET_2D_ARRAY ||
+ insn->tex.target == TEX_TARGET_CUBE ||
+ insn->tex.target == TEX_TARGET_CUBE_ARRAY) {
+ t
v1: - remove one occurence of TEX_TARGET_CUBE_ARRAY
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 104 +
1 file changed, 104 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index ae0dd78..22f2f5d 100644
--- a/src
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 50 ++
1 file changed, 50 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 7d77ca3
because we expose 8 images.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
b/src/gallium/drivers/nouveau/nvc0
MS images have to be handled explicitly and I don't plan to implement
them for now.
v1: - check that sample_count > 1
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/nouv
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 25 --
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 63fe9c0
views at bind time
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 5 +-
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 4 +
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 23 -
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 108
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 76 +-
.../nouveau/codegen/nv50_ir_lowering_nvc0.h| 2 +
2 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0
-1 --dmesg tests/deqp_gles3.py -t pbo gm107-pbo
[504/504] pass: 504 |
Thank you for running Piglit!
I think it's not bad! :)
-ilia
On Tue, Jul 19, 2016 at 4:15 PM, Samuel Pitoiset
wrote:
MS images have to be handled explicitly and I don't plan to implement
them for now.
v1: - che
e the tex handles area size in the driver")
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
b/src/galli
This fixes a regression introduced in
1da704a94c57aa0b0cf8faaa3236fe47dfb8f88c because the offset has moved
from 0x180 to 0x1a0, and the macros have to be re-compiled.
Fixes: 1da704a ("nvc0: increase the tex handles area size in the driver")
Signed-off-by: Samuel Pitoiset
---
s
This patch introduces the following regressions:
bin/fcc-read-to-pbo-after-clear -auto
bin/gl-2.1-pbo -auto -fbo
bin/fbo-pbo-readpixels-small -auto
bin/pbo-read-argb -auto
bin/pbo-readpixels-small -auto
bin/mesa_pack_invert-readpixels -auto -fbo
Tested on Fermi (GF119).
On 07/16/2016 09:09
On 07/22/2016 02:14 PM, Ilia Mirkin wrote:
You said earlier that pbo-readpixels-small worked with this patch on
Fermi :( Oh well.
It worked, but maybe an other issue has happened in the meantime :/
On Jul 22, 2016 5:39 AM, "Samuel Pitoiset" mailto:samuel.pitoi...@gmail.c
It's actually legal to have neg modifiers on both sources.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/no
On 07/23/2016 02:53 AM, Ilia Mirkin wrote:
No, it's not. But if the real op is OP_SUB, then the logic is a bit
different, since there's an implied extra neg on src(1).
Right, it's legal but for OP_SUB only.
On Fri, Jul 22, 2016 at 7:47 PM, Samuel Pitoiset
wrote:
It'
It's illegal to have neg modifiers on both sources for OP_ADD,
and it's illegal to have OP_SUB with just src0 neg.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/s
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 45 ++---
1 file changed, 9 insertions(+), 36 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 8abf1b5..25a5a8e
Mon, Jul 25, 2016 at 6:17 PM, Samuel Pitoiset
wrote:
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 45 ++---
1 file changed, 9 insertions(+), 36 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
b/src/gallium/driv
On 07/26/2016 12:24 AM, Ilia Mirkin wrote:
On Mon, Jul 25, 2016 at 6:21 PM, Samuel Pitoiset
wrote:
On 07/26/2016 12:20 AM, Ilia Mirkin wrote:
Sounds reasonable. Pretty sure those NV_VRAM_DOMAIN thingies should
just be txc->domain. With that fixed,
IIRC, this NV_VRAM_DOMAIN thing
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 25a5a8e..40a9c93 100644
--- a/src
PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0.
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 ++
.../nouveau/codegen/nv50_ir_lowering_gm107.h | 11
.../nouveau/codegen/nv50_ir_target_gm107.cpp
code and so the
number of changed lines is relatively small.
All piglit tests pass except
spec/arb_tessellation_shader/execution/tes-input/tes-input-gl_clipdistance
which also fails on previous generations, and has to be fixed at some point.
Heaven looks fine as well.
Please review,
Thanks!
S
This exposes OpenGL 4.1 on Maxwell (tested on GM107 and GM206).
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0
The number of outputs patch (limited to 255) has moved in the TCP
header, but blob seems to also set the old position. Also, the high
8-bits are now located inbetween the min/max parallel output read
address at position 20.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0
On 07/27/2016 01:32 AM, Ilia Mirkin wrote:
On Tue, Jul 26, 2016 at 6:53 PM, Samuel Pitoiset
wrote:
The number of outputs patch (limited to 255) has moved in the TCP
header, but blob seems to also set the old position. Also, the high
8-bits are now located inbetween the min/max parallel
On 07/27/2016 01:24 AM, Ilia Mirkin wrote:
On Tue, Jul 26, 2016 at 6:53 PM, Samuel Pitoiset
wrote:
PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0.
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33
On 07/27/2016 03:45 PM, Ilia Mirkin wrote:
On Wed, Jul 27, 2016 at 9:42 AM, Emil Velikov wrote:
On 8 June 2016 at 18:08, Samuel Pitoiset wrote:
This fixes a lot of flickering in The Talos Principle on Fermi+
(tested on both GF119 and GK106). My guess is that some indices
and/or some vertex
This exposes OpenGL 4.1 on Maxwell (tested on GM107 and GM206).
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0
PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0.
v1: make NVC0LegalizeSSA::bld as protected attribute
Signed-off-by: Samuel Pitoiset
---
.../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 ++
.../nouveau/codegen/nv50_ir_lowering_gm107.h | 8
f-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 5fc2753..ae21789 100644
--- a/src/gallium/drivers/nouveau/
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 52 ++
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 3 ++
3 files changed, 56 insertions(+)
diff --git a/src/gallium/drivers
On nvc0, a counter can up to 6 sources instead of only one
for nve4+. This fixes a crash when a counter uses more than
one source.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src
Signed-off-by: Samuel Pitoiset
---
src/mesa/state_tracker/st_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 4207cb6..25042fb 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa
This will be used by GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset
---
src/gallium/auxiliary/hud/hud_driver_query.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 25 +
src/gallium/include/pipe/p_defines.h | 12 +++-
3 files
This will be used for the GL_FLOAT counter type of
AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset
---
src/gallium/include/pipe/p_defines.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index c34c3c0
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
index e38744a..258b755 100644
--- a/src
Signed-off-by: Samuel Pitoiset
---
src/gallium/include/pipe/p_defines.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 8f20974..e8a6f1a 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium
This can be used to check if a query is unable to start.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/freedreno/freedreno_query.c| 4 ++--
src/gallium/drivers/freedreno/freedreno_query.h| 2 +-
src/gallium/drivers/freedreno/freedreno_query_hw.c | 3 ++-
src/gallium/drivers
This adds two groups of queries.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 4
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 5 +
2 files changed, 9 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
b/src/gallium
This will be used to sort counters per group for
GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset
---
src/gallium/include/pipe/p_defines.h | 7 +++
src/gallium/include/pipe/p_screen.h | 11 +++
2 files changed, 18 insertions(+)
diff --git a/src/gallium/include/pipe
From: Christoph Bumiller
This is based on the original patch of Christoph Bumiller.
(source: http://people.freedesktop.org/~chrisbmr/perfmon.diff)
V2: (Samuel Pitoiset)
- Fix compilation
- Improve the original code
- Rewrite some parts of the original code
Signed-off-by: Samuel Pitoiset
Hi,
As part of my Google Summer of Code 2014, I implemented
GL_AMD_performance_monitor for Nouveau using the state tracker of Gallium.
Currently, only MP counters for NVC0+ (fermi) are exposed through this
extension. At the end of my project, graphics counters for NV50 (tesla) will be
available f
501 - 600 of 5029 matches
Mail list logo
