Emit it on all platforms since gen7.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index
I got reviews and fixed the patches locally, but ended up merging the
ones that I sent originally to the list. This patch fixes those
mistakes.
Fixes: 78c125af3904c539ea69bec2dd9fdf7a5162854f
Signed-off-by: Rafael Antognolli
Cc: Jason Ekstrand
---
src/intel/vulkan/anv_private.h | 1 -
src
Emit it on all platforms since gen7.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/genX_cmd_buffer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 3691b4bdec9..0e8c9ee7c46 100644
more
consistent accross all platforms. Also, at least the hardware won't try
to read push constants that are not there anymore.
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Rafael Antognolli (4):
anv/gen10: Emit CS stall and mark push constants dirty.
i965/gen10: Use CS Stall inste
Ugh, I had to read this change many times to understand it, but I do
think it makes sense. The comments in the code helped a lot too.
Reviewed-by: Rafael Antognolli
On Mon, Jan 29, 2018 at 06:25:30PM +0200, Andres Gomez wrote:
> The emission of vertex attributes corresponding to dvec3 and dv
The first 2 patches of this series should be added to branch 18.0 too.
On Fri, Jan 26, 2018 at 11:32:38AM -0800, Rafael Antognolli wrote:
> Fixes: ca19ee33d7d39cb89d948b1c983763065975ce5b
> Signed-off-by: Rafael Antognolli
> Cc: Kenneth Graunke
> ---
> src/mesa/d
17.4 is actually 18.0.
Signed-off-by: Rafael Antognolli
Cc: "18.0" mesa-sta...@lists.freedesktop.org
---
docs/relnotes/17.4.0.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
index 412c0fc455e..6bebb514bd2 100644
--- a/doc
Gen10 seems pretty stable so far, so there's no reason to keep this
message.
Signed-off-by: Rafael Antognolli
Cc: Kenneth Graunke
Cc: "18.0" mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_context.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/s
Gen10 seems pretty stable so far, remove "alpha support" message.
Signed-off-by: Rafael Antognolli
Cc: Jason Ekstrand
Cc: "18.0" mesa-sta...@lists.freedesktop.org
---
src/intel/vulkan/anv_device.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --gi
ilable.
Signed-off-by: Rafael Antognolli
Cc: Ben Widawsky
---
This patch still needs more testing (only ran it through CI and also did
some basic tests on my machine to make sure it's not breaking anything).
src/intel/genxml/gen10.xml | 8
src/in
to something other than VFCOMP_STORE_SRC."
Since we set the component 1 to VFCOMP_STORE_0 on gen8+, and
VFCOMP_STORE_IID on gen5+, and we are not using components 2 and 3,
let's also set them to VFCOMP_STORE_0.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h |
On Fri, Sep 08, 2017 at 08:32:05AM -0700, Marathe, Yogesh wrote:
> > -Original Message-
> > From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
> > Sent: Friday, September 8, 2017 8:28 PM
> > To: Marathe, Yogesh
> > Cc: Tomasz Figa ; Antognolli, Rafael
> > ; Janes, Mark A ;
> > mesa-dev@l
On Tue, Oct 02, 2018 at 07:16:01PM +0300, asimiklit.w...@gmail.com wrote:
> From: Andrii Simiklit
>
> I guess that when we calculating the width0, height0, depth0
> to use for function 'intel_miptree_create' we need to consider
> the 'base level' like it is done in the 'intel_miptree_create_for_t
ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the
right thing and use the enum.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965
Starting in gen11, we have 3 more dwords used for Bindless Sampler State
pointer and size.
Cc: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dr
Please ignore this patch, Jordan's version is the correct one.
On Wed, Oct 10, 2018 at 01:30:52PM -0700, Rafael Antognolli wrote:
> Starting in gen11, we have 3 more dwords used for Bindless Sampler State
> pointer and size.
>
> Cc: Anuj Phogat
>
> ---
>
OUT_BATCH(0);
>}
> + if (devinfo->gen >= 10) {
> + OUT_BATCH(1);
> + OUT_BATCH(0);
> + OUT_BATCH(0);
> + }
Reviewed-by: Rafael Antognolli
>ADVANCE_BATCH();
> } else if (devinfo->gen >= 6) {
>
On Wed, Oct 10, 2018 at 01:39:25PM -0700, Jordan Justen wrote:
> Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on
> Skylake."
> Signed-off-by: Jordan Justen
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/src
On Wed, Oct 10, 2018 at 02:04:11PM -0700, Jordan Justen wrote:
> On 2018-10-10 13:45:13, Rafael Antognolli wrote:
> > On Wed, Oct 10, 2018 at 01:39:25PM -0700, Jordan Justen wrote:
> > > Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on
> > &g
ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the
right thing and use the enum.
v2: fix intel_miptree_finish_depth too (Caio)
Reviewed-by: Dylan Baker
Reviewed-by: Caio Marcelo de Oliveira Filho
Reviewed-by: Jason Ekstrand
---
I just added the finish_depth() fix in the sa
On Wed, Oct 10, 2018 at 05:00:33PM -0700, Jordan Justen wrote:
> On 2018-10-10 14:38:23, Rafael Antognolli wrote:
> > On Wed, Oct 10, 2018 at 02:04:11PM -0700, Jordan Justen wrote:
> > > On 2018-10-10 13:45:13, Rafael Antognolli wrote:
> > > > On Wed, Oct 10, 20
ed that point, then things should be fine.
As an extra thing, I think the test could additionally check that
everything rendered correctly (check some colors from the framebuffer).
Anyway, just some ideas.
Thanks,
Rafael
> Regards,
> Andrii.
> On Mon, Oct 8, 2018 at 11:46 PM Rafael
On Wed, Oct 17, 2018 at 06:08:34PM +0300, Danylo Piliaiev wrote:
> Signed-off-by: Danylo Piliaiev
> ---
> src/intel/tools/intel_sanitize_gpu.c | 38 +++-
> 1 file changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/src/intel/tools/intel_sanitize_gpu.c
> b/src/int
ignore blorp. The only primitive it emits is
3DPRIM_RECTLIST, and since it's not listed in the workarounds, we can
safely leave preemption enabled when it happens. Or it will be disabled
by a previous 3DPRIMITIVE, which should be fine too.
Signed-off-by: Rafael Antognolli
Cc: Kenneth Gr
Re-sending the series, this time adding preemption support only to i965,
since We still don't have vulkan tests for this.
The proposed piglit test for this series can be found here:
https://gitlab.freedesktop.org/rantogno/piglit/commits/review/context_preemption_v2
Cc: Kenneth Graunke
R
Set bit when initializing context.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_defines.h | 5
src/mesa/drivers/dri/i965/brw_state.h| 3 ++-
src/mesa/drivers/dri/i965/brw_state_upload.c | 25
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen10.xml | 8
src/intel/genxml/gen11.xml | 8
src/intel/genxml/gen9.xml | 8
3 files changed, 24 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index abd5da297d6..acded759335
On Mon, Oct 29, 2018 at 05:29:10PM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2018-10-29 17:19:53)
> > +void
> > +brw_enable_obj_preemption(struct brw_context *brw, bool enable)
> > +{
> > + const struct gen_device_info *devinfo = &brw->screen->
On Tue, Oct 30, 2018 at 04:32:54PM -0700, Kenneth Graunke wrote:
> On Monday, October 29, 2018 10:19:54 AM PDT Rafael Antognolli wrote:
> > Gen9 hardware requires some workarounds to disable preemption depending
> > on the type of primitive being emitted.
> >
> > We imp
Reviewed-by: Rafael Antognolli
On Fri, Jul 06, 2018 at 11:02:05AM +0100, Lionel Landwerlin wrote:
> We were not properly writing page tables when the virtual address
> range spans multiple subtrees of the tables.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tool
Using -vv will increase the verbosity, by printing the ppgtt mappings as
they get written into the aub file.
Cc: Lionel Landwerlin
---
src/intel/tools/intel_dump_gpu.c | 25 -
src/intel/tools/intel_dump_gpu.in | 6 ++
2 files changed, 30 insertions(+), 1 deletion(-)
Reviewed-by: Rafael Antognolli
On Thu, Jul 12, 2018 at 11:46:12AM -0700, Eric Anholt wrote:
> ---
> src/intel/tools/intel_dump_gpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/intel/tools/intel_dump_gpu.c
> b/src/intel/tools/intel_dump_gpu.c
&g
On Wed, Jul 18, 2018 at 06:21:32PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aub_write.c | 45 ++---
> 1 file changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/src/intel/tools/aub_write.c b/src/intel/tools
On Thu, Jul 19, 2018 at 10:14:32AM +0100, Lionel Landwerlin wrote:
> On 18/07/18 21:58, Rafael Antognolli wrote:
> > On Wed, Jul 18, 2018 at 06:21:32PM +0100, Lionel Landwerlin wrote:
> > > Signed-off-by: Lionel Landwerlin
> > > ---
> > >
I was thinking about the patch. I didn't look deeply into the one that
removes the command execution stuff, but for the rest of the series,
Acked-by: Rafael Antognolli
Sorry for being ambiguous :P
On Thu, Jul 19, 2018 at 10:12:57AM +0100, Lionel Landwerlin wrote:
> Was that for t
t;
> Suggested-by: Rafael Antognolli
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
> ---
> src/intel/tools/intel_dump_gpu.in | 19 ---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/tools/in
onfiguration through a temporary file that is
> deleted once the command line passes to intel_dump_gpu has exited.
Nice, I noticed this weird behavior too, thanks for fixing.
Reviewed-by: Rafael Antognolli
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/intel_dump_gpu
Hi Vadym,
Ken and Ian explained a bit the situation on this one to me, and it
looks like neither of them are really against this patch. So unless
someone else raise any concern, I'll ack and push the patch later today.
Thanks for fixing this.
Rafael
On Thu, Jul 26, 2018 at 04:04:29PM +0300, Vad
On Mon, Jul 30, 2018 at 04:28:37PM +0100, Lionel Landwerlin wrote:
> Gen10+ has an additional bit in MI_BATCH_BUFFER_END to signal the end
> of the context image.
Cool, I see you are also adding a couple missing commands and noops into
the gen10+ contexts.
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:13AM +0100, Lionel Landwerlin wrote:
> Up to now we've been lucky that the buffer returned was always exactly
> at the address we requested.
Looks like this needs to land, even if the rest of the series doesn't.
Reviewed-by: Rafael Antognolli
>
Looks like no functional change, and it's needed by the ui tool, so
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:19AM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aub_read.c | 307 +
On Thu, Aug 02, 2018 at 10:39:20AM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/util/rb_tree.h | 36
> 1 file changed, 36 insertions(+)
>
> diff --git a/src/util/rb_tree.h b/src/util/rb_tree.h
> index c77e9255ea2..df1a4197b8a
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:22AM +0100, Lionel Landwerlin wrote:
> ---
> src/intel/tools/aub_write.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/intel/tools/aub_write.h b/src/intel/tools/aub_write.h
> index b42167
This also looks like a harmless and useful refactory.
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:21AM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aub_mem.c | 391
> src
page ?
> + (struct gen_batch_decode_bo) { .map = page->data, .addr =
> page->phys_addr, .size = 4096 } :
Looks like we are starting to use gen_batch_decode_bo as a generic
address pointer now (to both physical, virtual or aub data memory), so
maybe at some point we might wan
Ugh, I just replied with the whole message without cutting it out, so in
case it doesn't reach the ML, this is what I wanted to say:
On Mon, Aug 06, 2018 at 11:19:20AM -0700, Rafael Antognolli wrote:
> I would change the commit summary line to make it clear we are importing
> imgui co
Patches 13 and 14 are:
Acked-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:25AM +0100, Lionel Landwerlin wrote:
> A graphical user interface version of aubinator.
> Allows you to :
>
>- simultaneously look at multiple points in the aub file (using all
> the goodne
On Tue, Aug 07, 2018 at 06:35:20PM +0100, Lionel Landwerlin wrote:
> A graphical user interface version of aubinator.
> Allows you to :
>
>- simultaneously look at multiple points in the aub file (using all
> the goodness of the existing decoding in aubinator)
>
>- edit an aub file
>
On Tue, Aug 07, 2018 at 06:35:13PM +0100, Lionel Landwerlin wrote:
> v2: Add helper to make iterators more readable (Rafael)
> Fix rev iterator bug (Rafael)
>
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
> ---
> src/u
Reviewed-by: Rafael Antognolli
On Tue, Aug 07, 2018 at 06:35:16PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/meson.build | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/tools
On Tue, Aug 07, 2018 at 06:35:18PM +0100, Lionel Landwerlin wrote:
> When we map a PPGTT buffer into a continous address space of aubinator
> to be able to inspect it, we currently add it to the list of BOs to
> unmap once we're finished. An optimization we can apply it to look up
> that list befor
I'm not that familiar with this code yet, so take this review with a
grain of salt, but it looks good to me.
Reviewed-by: Rafael Antognolli
Just a few comments below but nothing really important.
On Tue, Aug 07, 2018 at 06:35:21PM +0100, Lionel Landwerlin wrote:
> Signed-off-by
const_br(x + (const_idx + stages[s].const_rd_length) *
> alloc_delta,
> + y + row_height);
> +
> + char label[40];
> + snprintf(label, sizeof(label), "%s: ", stage_names[s]);
> + draw_list->AddText(alloc_pos, ImGui::
FFE0U and it looks like unexpected behavior for
> me:
> iter_group_offset_bits(iter, iter->group_iter + 1) < 0xFFE0U;
That's fine, I think the original commit message is good enough to
understand this change. Feel free to add this extra bit too if you want,
but I don't th
so it seemed reasonable to check for that, considering we
can return -1, but I agree that printing "unknown instruction" would be
better.
> -
> Lionel
>
>
> On 10/08/18 16:48, Rafael Antognolli wrote:
> > On Thu, Aug 09, 2018 at 03:00:30PM +0300, andrey simiklit wrot
On Tue, Aug 14, 2018 at 03:36:18PM +0100, Lionel Landwerlin wrote:
> On 14/08/18 12:55, asimiklit.work wrote:
> > Hi Lionel,
> > > Hi Andrii,
> > >
> > > Again sorry, I don't think this is the right fix.
> > > I'm sending another patch to fix the parsing of
> > > MI_BATCH_BUFFER_START which seems
ring_name is " + " (e.g. rcs0). So we need to
first compare the class name only, then get the instance id.
Without this, INSTDONE is not being decoded.
Signed-off-by: Rafael Antognolli
Cc: Chris Wilson
---
src/intel/tools/aubinator_error_decode.c | 2 +-
1 file changed, 1 inser
---
src/intel/genxml/gen10.xml | 18 ++
src/intel/genxml/gen11.xml | 18 ++
src/intel/genxml/gen7.xml | 20
src/intel/genxml/gen75.xml | 22 ++
src/intel/genxml/gen8.xml | 18 ++
src/intel/genxml/gen9.xml |
Decode SC_INSTDONE, ROW_INSTDONE and SAMPLER_INSTDONE.
---
src/intel/tools/aubinator_error_decode.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index db880d74a9e..9abd05fd75a 100644
--- a/src
---
src/intel/genxml/gen10.xml | 23 +++
src/intel/genxml/gen11.xml | 23 +++
src/intel/genxml/gen7.xml | 22 ++
src/intel/genxml/gen75.xml | 25 +
src/intel/genxml/gen8.xml | 23 +++
src/inte
---
src/intel/genxml/gen10.xml | 27 +++
src/intel/genxml/gen11.xml | 27 +++
src/intel/genxml/gen7.xml | 19 +++
src/intel/genxml/gen75.xml | 17 +
src/intel/genxml/gen8.xml | 24
src/intel/
On Wed, Mar 21, 2018 at 02:06:12PM -0700, Matt Turner wrote:
> We all know the platform names, and I don't want to update this list
> continually.
Reviewed-by: Rafael Antognolli
> ---
> src/intel/tools/aubinator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
&
On Wed, Mar 21, 2018 at 02:06:14PM -0700, Matt Turner wrote:
> From: Anuj Phogat
>
> On gen11+ AUX_HIZ is not a supported value for surfaces being
> sampled by the 3D sampler.
Reviewed-by: Rafael Antognolli
> ---
> src/intel/dev/gen_device_info.c | 1 +
> 1 file
Matches the bspec.
Reviewed-by: Rafael Antognolli
On Wed, Mar 21, 2018 at 02:06:20PM -0700, Matt Turner wrote:
> From: Anuj Phogat
>
> ---
> include/pci_ids/i965_pci_ids.h | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/include/pci_ids/i965_pci_id
On Tue, Mar 27, 2018 at 11:16:37AM -0700, Jason Ekstrand wrote:
> On Thu, Mar 8, 2018 at 8:49 AM, Rafael Antognolli
>
> wrote:
>
> On Gen10, whenever we do a fast clear, blorp will update the clear color
> state buffer for us, as long as we set the clear color addre
On Tue, Mar 27, 2018 at 11:19:43AM -0700, Jason Ekstrand wrote:
> On Tue, Mar 27, 2018 at 4:37 AM, Pohjolainen, Topi
>
> wrote:
>
> On Thu, Mar 08, 2018 at 08:49:06AM -0800, Rafael Antognolli wrote:
> > On Gen10, when emitting the surface state, use the value stored
ned-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Topi Pohjolainen
---
src/intel/vulkan/anv_image.c | 23 ++-
src/intel/vulkan/anv_private.h | 4 ++--
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/in
Another revision, hopefully with all the last suggestions included.
This revision of this series can be found here:
https://cgit.freedesktop.org/~rantogno/mesa/log/?h=cnl/fast_clear_address_v5
Cc: Jason Ekstrand
Cc: Jordan Justen
Cc: "Pohjolainen, Topi"
Rafael Antognolli (19):
centralize everything in blorp, hopefully removing a lot of code
duplication. It also allows us to have a similar behavior on gen < 9 and
gen >= 10.
v5: s/we/we are/ (Jordan)
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/blorp/blorp_genX_
h the address. But if they are in the higher 32 bits, they get
discarded.
On Gen10 we have fields that share space with the higher 16 bits of the
address too. This commit makes sure those fields don't get discarded.
v5: Remove spurious whitespace (Jason).
Signed-off-by: Rafael Antognolli
R
t;Clear Color Address"
to "Clear Value Address" and use it for both color and depth. Do the
same for the high bits.
TODO: add support for multiple addresses at the same position in the
xml.
v2: Combine high and low order bits into a single address field.
Signed-off-by: Rafael Antognoll
We only need to copy the clear color from the state buffer to the
inlined surface state when doing a resolve.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/blorp/blorp_genX_exec.h | 13 +
1 file changed, 9 insertions(+), 4
.
- Bring back missing offset increment to init_fast_clear_color().
[jordan.l.jus...@intel.com: isl_device_init changes]
Signed-off-by: Rafael Antognolli
Signed-off-by: Jordan Justen
---
src/intel/blorp/blorp_genX_exec.h | 5 +++--
src/intel/isl/isl.c| 4
src/intel/isl/isl.h
.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jordan Justen
---
src/intel/isl/isl.h | 9 +
src/intel/isl/isl_surface_state.c | 18 ++
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index
v5: Split genxml changes into its own commit (Jason).
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen10.xml | 8
src/intel/genxml/gen11.xml | 10 ++
2 files changed, 18 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index
helper to extract clear color from attachment (Jason)
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/vulkan/anv_image.c | 17 +
src/intel/vulkan/anv_private.h | 5
src/intel/vulkan/genX_cmd_buffer.c | 52
struct
v5: Unreference clear color bo (Jordan)
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 16
2 files changed, 33
: Rafael Antognolli
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d11ae65243f..89074a64930 100644
available.
- let core blorp update the clear color, but also update it when we
skip a fast clear depth.
v5: Better subject (Jordan).
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 11 +++
src/mesa/drivers/dri/i965/brw_clear.c | 22 ++
2
Extract the code from color_attachment_compute_aux_usage, so we can
later reuse it to update the clear color state buffer.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/vulkan/anv_private.h | 20
src/intel/vulkan
Instead of updating the clear color in anv before a resolve, just let
blorp handle that for us during fast clears.
v5: Update comment about HiZ clear color (Jordan).
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/vulkan/anv_blorp.c
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
v4: Use the clear color offset from the clear_color_bo, when available.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by
Store the default clear address for HiZ fast clears on a global bo, and
point to it when needed.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/vulkan/anv_device.c | 19 +++
src/intel/vulkan/anv_image.c | 10
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.
v4: Remove redundant #if clause for GEN <= 10 (Jason)
v5: Move flush after the reloc, and keep lower bits (Topi).
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Re
d-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/blorp/blorp_genX_exec.h| 4
src/intel/isl/isl.h | 7 +++
src/intel/isl/isl_surface_state.c| 21 +++--
src/intel/v
In a follow up patch, we make use of clear_color_bo, which is in
mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the
same thing on both aux buffers, just use aux_buf already.
v5: Add aux_buf to brw_wm_surface_state too.
Signed-off-by: Rafael Antognolli
---
src/mesa/d
On Tue, Apr 03, 2018 at 06:05:06PM +0300, Pohjolainen, Topi wrote:
> On Thu, Mar 29, 2018 at 10:58:40AM -0700, Rafael Antognolli wrote:
> > gen10 can emit the clear color by setting it on a buffer somewhere, and
> > then adding only the address to the surface state.
> >
On Tue, Apr 03, 2018 at 06:53:18PM +0300, Pohjolainen, Topi wrote:
> On Tue, Apr 03, 2018 at 06:50:09PM +0300, Pohjolainen, Topi wrote:
> > On Tue, Apr 03, 2018 at 08:43:54AM -0700, Rafael Antognolli wrote:
> > > On Tue, Apr 03, 2018 at 06:05:06PM +0300, Pohjolainen, Topi wro
On Fri, Apr 06, 2018 at 06:07:52PM +0300, Topi Pohjolainen wrote:
> Otherwise even the clear color gets initialised to 0xFF. This
> allows enabling of color fast clears on ICL without regressing
> multisampling tests.
>
> CC: Rafael Antognolli
> CC: Jason Ekstrand
> CC: N
On Tue, Aug 13, 2019 at 05:50:30PM +0200, Mauro Rossi wrote:
> Instead of "genX_bits.h" use "genxml/genX_bits.h"
> as already done in other similar cases
>
> Besides being more correct, it also fixes building error in Android.
Ugh, sorry for that.
Reviewed
I failed to initialize it on the other cases in GEN11 and it was causing
a segfault when going through anv_DestroyDevice, if compiled with
valgrind.
Fixes: 7bc022b4bbc ("anv/gen11: Emit SLICE_HASH_TABLE when pipes are
unbalanced.)
---
src/intel/vulkan/genX_state.c | 4 ++--
1
, 2019 at 5:45 PM Rafael Antognolli
>
> wrote:
>
> I failed to initialize it on the other cases in GEN11 and it was causing
> a segfault when going through anv_DestroyDevice, if compiled with
> valgrind.
>
> Fixes: 7bc022b4bbc ("anv/gen11
This param is only available starting on kernel 4.16. Use a default
value of 0 if it is not found instead.
Cc: Jordan Justen
Cc: Mark Janes
---
src/intel/dev/gen_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen
This commit might also need a:
Fixes: 96e1c945f2b ("i965: Move device info initialization to common
code")
On Mon, Aug 19, 2019 at 12:28:55PM -0700, Rafael Antognolli wrote:
> This param is only available starting on kernel 4.16. Use a default
> value of 0 if
On Mon, Aug 19, 2019 at 11:25:38PM +0200, Lionel Landwerlin wrote:
> On 19/08/2019 21:28, Rafael Antognolli wrote:
> > This param is only available starting on kernel 4.16. Use a default
> > value of 0 if it is not found instead.
>
>
> I trace the p
Depth fast clears were unrestricted, meaning they were enabled on every
hardware generation. However, gen11+ requires some extra code to make it
work properly.
---
src/gallium/drivers/iris/iris_clear.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers/iris/iris_clear.c
On Wed, Apr 17, 2019 at 09:04:09AM -0700, Kenneth Graunke wrote:
> On Wednesday, April 17, 2019 7:16:28 AM PDT Topi Pohjolainen wrote:
> > From: Rafael Antognolli
> >
> > Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.
> >
> > CC: Anuj Phogat
>
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