[Mesa-dev] [PATCH] ac/nir: generate correct instruction for atomic min/max on unsigned images

--- src/amd/common/ac_nir_to_llvm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 3d635d4206..870731f3eb 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -3667,1

[Mesa-dev] [PATCH V2] ac/nir: generate correct instruction for atomic min/max on unsigned images

v2: fix silly typo Cc: "17.2 17.3" --- src/amd/common/ac_nir_to_llvm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 3d635d4206..06937d684b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/a

[Mesa-dev] [PATCH] radv: restore previous stencil reference after depth-stencil clear

Cc: mesa-sta...@lists.freedesktop.org --- src/amd/vulkan/radv_meta_clear.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index b42ecedfc9..98fb8fa6a7 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/r

[Mesa-dev] [PATCH] radv: fix multisample image copies

Previously before fb077b0728, the LOD parameter was being used in place of the sample index, which would only copy the first sample to all samples in the destination image. After that multisample image copies wouldn't copy anything from my observations. Fix this properly by copying each sample in

Re: [Mesa-dev] [PATCH] radv: fix multisample image copies

On 18/04/18 22:56, Dave Airlie wrote: On 18 April 2018 at 00:31, Matthew Nicholls wrote: Previously before fb077b0728, the LOD parameter was being used in place of the sample index, which would only copy the first sample to all samples in the destination image. After that multisample image

Re: [Mesa-dev] [PATCH v2] radv: fix multisample image copies

I've verified the V2 of my patch does still fix the original issue I was seeing. Thanks a bunch. Matthew. On 27/04/18 12:26, Samuel Pitoiset wrote: Matthew, can you double-check if v2 still fixes the issue for you? Thanks! On 04/27/2018 01:23 PM, Samuel Pitoiset wrote: From: Ma

[Mesa-dev] [PATCH] radv: emit a cache flush before enabling predication

Otherwise cache flushes could get conditionally disabled while still clearing the flush_bits, and thus flushes due to application pipeline barriers may never get executed. Cc: mesa-sta...@lists.freedesktop.org --- src/amd/vulkan/radv_meta_fast_clear.c | 2 ++ 1 file changed, 2 insertions(+) diff

[Mesa-dev] [PATCH] radv: remove predication on cache flushes

This can lead to a situation where cache flushes could get conditionally disabled while still clearing the flush_bits, and thus flushes due to application pipeline barriers may never get executed. Cc: mesa-sta...@lists.freedesktop.org --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/r